[PATCH v2 0/2] lib: sbi: Flush cache entries after writing PMP CSRs

[cp0613 at linux.alibaba.com]

From: Chen Pei <cp0613 at linux.alibaba.com>

As the privileged specification states, after writing to the PMP CSRs,
a SFENCE.VMA or HFENCE.GVMA instruction should be executed with rs1=x0
and rs2=x0 to flush all address translation cache entries.

The original implementation does not cover all possible cases. For
example, the unconfigure and map_range/unmap_range functions of
sbi_hart_protection calls pmp_set but does not execute the SFENCE.VMA
instruction. This patch covers these cases, ensuring that dbtr, sse, and
other modules can safely update pmpcfg.

Considering the performance issues caused by flush all address translation
cache entries, sbi_hart_pmp_fence_vma is introduced to flush only the
entries corresponding to a given address and size.

Changes in v2:
 - Introduce sbi_hart_pmp_fence_vma
 - Use sbi_hart_pmp_fence_vma when calling map_range/unmap_range in
   sbi_hart_protection to avoid performance issues caused by using
   sbi_hart_pmp_fence_all.

Chen Pei (2):
  lib: sbi: Introduce sbi_hart_pmp_fence_vma
  lib: sbi: Flush cache entries after writing PMP CSRs

 include/sbi/sbi_hart_pmp.h       |  3 ++-
 lib/sbi/sbi_hart_pmp.c           | 41 ++++++++++++++++++++++++++++----
 platform/generic/eswin/eic770x.c |  2 +-
 3 files changed, 40 insertions(+), 6 deletions(-)

-- 
2.50.1