Functional testing of mainline vchiq driver
Michael Zoran
mzoran at crowfest.net
Tue Oct 25 16:22:27 PDT 2016
On Tue, 2016-10-25 at 14:52 -0700, Michael Zoran wrote:
> On Tue, 2016-10-25 at 14:45 -0700, Michael Zoran wrote:
> > On Tue, 2016-10-25 at 23:20 +0200, Stefan Wahren wrote:
> > >
> > > thanks, here are my steps to get the driver working:
> > >
> > > * checkout Greg's staging-testing tree
> > > * applied "staging: vc04_services: Remove dmac_map_area"
> > > * remove BROKEN in drivers/staging/vc04_services/Kconfig
> > > * add the following node to arch/arm/boot/dts/bcm283x.dtsi
> > >
> > > vchiq: vchiq at 7e00b840 {
> > > compatible = "brcm,bcm2835-vchiq";
> > > reg = <0x7e00b840 0xf>;
> > > interrupts = <0 2>;
> > > cache-line-size = <32>;
> > > firmware = <&firmware>;
> > > };
> > >
> > > * build kernel and dtb for Raspberry Pi B
> > >
> > >
>
> BTW, the downstream tree has an override for the cache-line-
> size. Did
> you perhaps try and add it to the device tree as well?
>
> bcm2708_common.dtsi:
>
> __overrides__ {
> cache_line_size = <&vchiq>, "cache-line-size:0";
> };
OK, I was able to boot a stock upstream kernel on a RPI-2.
The issue is the __overrides__ is needed.
I was able to run vchiq_test -f 10 perfectly with exact same
tree+patches.
Here is my bcm283x.dtsi file. Note the __overrides__ at the end.
#include <dt-bindings/pinctrl/bcm2835.h>
#include <dt-bindings/clock/bcm2835.h>
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
/* This include file covers the common peripherals and configuration
between
* bcm2835 and bcm2836 implementations, leaving the CPU configuration
to
* bcm2835.dtsi and bcm2836.dtsi.
*/
/ {
compatible = "brcm,bcm2835";
model = "BCM2835";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "earlyprintk console=ttyAMA0";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
timer at 7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
/* This could be a reference to
BCM2835_CLOCK_TIMER,
* but we don't have the driver using the
common clock
* support yet.
*/
clock-frequency = <1000000>;
};
dma: dma at 7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xf00>;
interrupts = <1 16>,
<1 17>,
<1 18>,
<1 19>,
<1 20>,
<1 21>,
<1 22>,
<1 23>,
<1 24>,
<1 25>,
<1 26>,
/* dma channel 11-14 share one irq
*/
<1 27>,
<1 27>,
<1 27>,
<1 27>,
/* unused shared irq for all
channels */
<1 28>;
interrupt-names = "dma0",
"dma1",
"dma2",
"dma3",
"dma4",
"dma5",
"dma6",
"dma7",
"dma8",
"dma9",
"dma10",
"dma11",
"dma12",
"dma13",
"dma14",
"dma-shared-all";
#dma-cells = <1>;
brcm,dma-channel-mask = <0x7f35>;
};
intc: interrupt-controller at 7e00b200 {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
watchdog at 7e100000 {
compatible = "brcm,bcm2835-pm-wdt";
reg = <0x7e100000 0x28>;
};
clocks: cprman at 7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
/* CPRMAN derives everything from the
platform's
* oscillator.
*/
clocks = <&clk_osc>;
};
rng at 7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
};
mailbox: mailbox at 7e00b800 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
#mbox-cells = <0>;
};
gpio: gpio at 7e200000 {
compatible = "brcm,bcm2835-gpio";
reg = <0x7e200000 0xb4>;
/*
* The GPIO IP block is designed for 3 banks of
GPIOs.
* Each bank has a GPIO interrupt for itself.
* There is an overall "any bank" interrupt.
* In order, these are GIC interrupts 17, 18,
19, 20.
* Since the BCM2835 only has 2 banks, the 2nd
bank
* interrupt output appears to be mirrored onto
the
* 3rd bank's interrupt signal.
* So, a bank0 interrupt shows up on 17, 20,
and
* a bank1 interrupt shows up on 18, 19, 20!
*/
interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart0: serial at 7e201000 {
compatible = "brcm,bcm2835-pl011", "arm,pl011",
"arm,primecell";
reg = <0x7e201000 0x1000>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
};
i2s: i2s at 7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x20>,
<0x7e101098 0x02>;
dmas = <&dma 2>,
<&dma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
spi: spi at 7e204000 {
compatible = "brcm,bcm2835-spi";
reg = <0x7e204000 0x1000>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c at 7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pixelvalve at 7e206000 {
compatible = "brcm,bcm2835-pixelvalve0";
reg = <0x7e206000 0x100>;
interrupts = <2 13>; /* pwa0 */
};
pixelvalve at 7e207000 {
compatible = "brcm,bcm2835-pixelvalve1";
reg = <0x7e207000 0x100>;
interrupts = <2 14>; /* pwa1 */
};
aux: aux at 0x7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
};
uart1: serial at 7e215040 {
compatible = "brcm,bcm2835-aux-uart";
reg = <0x7e215040 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
status = "disabled";
};
spi1: spi at 7e215080 {
compatible = "brcm,bcm2835-aux-spi";
reg = <0x7e215080 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi at 7e2150c0 {
compatible = "brcm,bcm2835-aux-spi";
reg = <0x7e2150c0 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm: pwm at 7e20c000 {
compatible = "brcm,bcm2835-pwm";
reg = <0x7e20c000 0x28>;
clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clock-rates = <10000000>;
#pwm-cells = <2>;
status = "disabled";
};
sdhci: sdhci at 7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
clocks = <&clocks BCM2835_CLOCK_EMMC>;
status = "disabled";
};
hvs at 7e400000 {
compatible = "brcm,bcm2835-hvs";
reg = <0x7e400000 0x6000>;
interrupts = <2 1>;
};
i2c1: i2c at 7e804000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e804000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c at 7e805000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e805000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pixelvalve at 7e807000 {
compatible = "brcm,bcm2835-pixelvalve2";
reg = <0x7e807000 0x100>;
interrupts = <2 10>; /* pixelvalve */
};
hdmi: hdmi at 7e902000 {
compatible = "brcm,bcm2835-hdmi";
reg = <0x7e902000 0x600>,
<0x7e808000 0x100>;
interrupts = <2 8>, <2 9>;
ddc = <&i2c2>;
clocks = <&clocks BCM2835_PLLH_PIX>,
<&clocks BCM2835_CLOCK_HSM>;
clock-names = "pixel", "hdmi";
status = "disabled";
};
usb: usb at 7e980000 {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
interrupts = <1 9>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_usb>;
clock-names = "otg";
};
v3d: v3d at 7ec00000 {
compatible = "brcm,bcm2835-v3d";
reg = <0x7ec00000 0x1000>;
interrupts = <1 10>;
};
vc4: gpu {
compatible = "brcm,bcm2835-vc4";
};
vchiq: vchiq at 7e00b840 {
compatible = "brcm,bcm2835-vchiq";
reg = <0x7e00b840 0xf>;
interrupts = <0 2>;
cache-line-size = <32>;
firmware = <&firmware>;
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
/* The oscillator is the root of the clock tree. */
clk_osc: clock at 3 {
compatible = "fixed-clock";
reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
clk_usb: clock at 4 {
compatible = "fixed-clock";
reg = <4>;
#clock-cells = <0>;
clock-output-names = "otg";
clock-frequency = <480000000>;
};
};
__overrides__ {
cache_line_size = <&vchiq>, "cache-line-size:0";
};
};
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