[PATCH 11/12] ARM: bcm2835: implement reset using watchdog

[Stephen Warren]

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
 arch/arm/cpu/arm1176/bcm2835/reset.c     |   18 +++++++++++----
 arch/arm/include/asm/arch-bcm2835/wdog.h |   37 ++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-bcm2835/wdog.h

diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/cpu/arm1176/bcm2835/reset.c
index 69c9577..8c37ad9 100644
--- a/arch/arm/cpu/arm1176/bcm2835/reset.c
+++ b/arch/arm/cpu/arm1176/bcm2835/reset.c
@@ -16,12 +16,20 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/wdog.h>
+
+#define RESET_TIMEOUT 10
 
 void reset_cpu(ulong addr)
 {
-	/*
-	 * We should probably use the WDT module here, but an unaligned
-	 * access will do the trick for now.
-	 */
-	readl(1);
+	struct bcm2835_wdog_regs *regs =
+		(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+	uint32_t rstc;
+
+	rstc = readl(&regs->rstc);
+	rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
+	rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
+
+	writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, &regs->wdog);
+	writel(BCM2835_WDOG_PASSWORD | rstc, &regs->rstc);
 }
diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h
new file mode 100644
index 0000000..d750a62
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm2835/wdog.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_TIMER_H
+#define _BCM2835_TIMER_H
+
+#define BCM2835_WDOG_PHYSADDR			0x20100000
+
+struct bcm2835_wdog_regs {
+	u32 unknown0[7];
+	u32 rstc;
+	u32 unknown1;
+	u32 wdog;
+};
+
+#define BCM2835_WDOG_PASSWORD			0x5a000000
+
+#define BCM2835_WDOG_RSTC_WRCFG_MASK		0x00000030
+#define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET	0x00000020
+
+#define BCM2835_WDOG_WDOG_TIMEOUT_MASK		0x0000ffff
+
+#endif
+
-- 
1.7.9.5