[PATCH 21/27] phy: rockchip-inno-usb2: Add RK3572 support
Cunhao Lu via B4 Relay
devnull+1579567540.qq.com at kernel.org
Wed Oct 21 09:11:18 PDT 2026
From: Cunhao Lu <1579567540 at qq.com>
Support both RK3572 USB2 PHY instances.
Signed-off-by: Cunhao Lu <1579567540 at qq.com>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 136 ++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 7d8a533f24aea..16a36e68cb6d3 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1544,6 +1544,49 @@ static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
return 0;
}
+static int rk3572_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg = rphy->phy_cfg->reg;
+ struct clk *refclk;
+ unsigned long rate;
+ u32 val;
+ int ret;
+
+ refclk = devm_clk_get(rphy->dev, "phyclk");
+ if (IS_ERR(refclk))
+ return PTR_ERR(refclk);
+ rate = clk_get_rate(refclk);
+ if (rate != 24000000 && rate != 26000000)
+ return -EINVAL;
+
+ ret = regmap_write(rphy->grf, reg + 0x0004,
+ GENMASK(18, 16) | (rate == 24000000 ? 2 : 6));
+ if (ret)
+ return ret;
+
+ ret = regmap_read(rphy->grf, reg + 0x0010, &val);
+ if (ret)
+ return ret;
+ if (val & BIT(13)) {
+ ret = regmap_write(rphy->grf, reg + 0x0010, BIT(29));
+ if (ret)
+ return ret;
+ ret = rockchip_usb2phy_reset(rphy);
+ if (ret)
+ return ret;
+ }
+
+ /* Set the normal line-state filter interval. */
+ ret = regmap_write(rphy->grf, reg + 0x0020, 0x30100);
+ if (ret)
+ return ret;
+ /* Increase HS voltage by 5.89% and double pre-emphasis current. */
+ ret = regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);
+ if (ret)
+ return ret;
+ return regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);
+}
+
static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
int ret;
@@ -2126,6 +2169,98 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3572_phy_cfgs[] = {
+ {
+ .reg = 0x0,
+ .num_ports = 1,
+ .phy_tuning = rk3572_usb2phy_tuning,
+ .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x00c0, 1, 1, 0, 1 },
+ .bvalid_det_st = { 0x00c4, 1, 1, 0, 1 },
+ .bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },
+ .idfall_det_en = { 0x00c0, 4, 4, 0, 1 },
+ .idfall_det_st = { 0x00c4, 4, 4, 0, 1 },
+ .idfall_det_clr = { 0x00c8, 4, 4, 0, 1 },
+ .idrise_det_en = { 0x00c0, 3, 3, 0, 1 },
+ .idrise_det_st = { 0x00c4, 3, 3, 0, 1 },
+ .idrise_det_clr = { 0x00c8, 3, 3, 0, 1 },
+ .ls_det_en = { 0x00c0, 0, 0, 0, 1 },
+ .ls_det_st = { 0x00c4, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x00c8, 0, 0, 0, 1 },
+ .disfall_en = { 0x00c0, 6, 6, 0, 1 },
+ .disfall_st = { 0x00c4, 6, 6, 0, 1 },
+ .disfall_clr = { 0x00c8, 6, 6, 0, 1 },
+ .disrise_en = { 0x00c0, 5, 5, 0, 1 },
+ .disrise_st = { 0x00c4, 5, 5, 0, 1 },
+ .disrise_clr = { 0x00c8, 5, 5, 0, 1 },
+ .utmi_avalid = { 0x0080, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x0080, 0, 0, 0, 1 },
+ .utmi_id = { 0x0080, 6, 6, 0, 1 },
+ .utmi_ls = { 0x0080, 5, 4, 0, 1 },
+ }
+ },
+ .chg_det = {
+ .cp_det = { 0x0080, 8, 8, 0, 1 },
+ .dcp_det = { 0x0080, 8, 8, 0, 1 },
+ .dp_det = { 0x0080, 9, 9, 1, 0 },
+ .idm_sink_en = { 0x0010, 5, 5, 1, 0 },
+ .idp_sink_en = { 0x0010, 5, 5, 0, 1 },
+ .idp_src_en = { 0x0010, 14, 14, 0, 1 },
+ .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 },
+ .vdm_src_en = { 0x0010, 7, 6, 0, 3 },
+ .vdp_src_en = { 0x0010, 7, 6, 0, 3 },
+ },
+ },
+ {
+ .reg = 0x2000,
+ .num_ports = 1,
+ .phy_tuning = rk3572_usb2phy_tuning,
+ .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x20c0, 1, 1, 0, 1 },
+ .bvalid_det_st = { 0x20c4, 1, 1, 0, 1 },
+ .bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },
+ .idfall_det_en = { 0x20c0, 4, 4, 0, 1 },
+ .idfall_det_st = { 0x20c4, 4, 4, 0, 1 },
+ .idfall_det_clr = { 0x20c8, 4, 4, 0, 1 },
+ .idrise_det_en = { 0x20c0, 3, 3, 0, 1 },
+ .idrise_det_st = { 0x20c4, 3, 3, 0, 1 },
+ .idrise_det_clr = { 0x20c8, 3, 3, 0, 1 },
+ .ls_det_en = { 0x20c0, 0, 0, 0, 1 },
+ .ls_det_st = { 0x20c4, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x20c8, 0, 0, 0, 1 },
+ .disfall_en = { 0x20c0, 6, 6, 0, 1 },
+ .disfall_st = { 0x20c4, 6, 6, 0, 1 },
+ .disfall_clr = { 0x20c8, 6, 6, 0, 1 },
+ .disrise_en = { 0x20c0, 5, 5, 0, 1 },
+ .disrise_st = { 0x20c4, 5, 5, 0, 1 },
+ .disrise_clr = { 0x20c8, 5, 5, 0, 1 },
+ .utmi_avalid = { 0x2080, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x2080, 0, 0, 0, 1 },
+ .utmi_id = { 0x2080, 6, 6, 0, 1 },
+ .utmi_ls = { 0x2080, 5, 4, 0, 1 },
+ }
+ },
+ .chg_det = {
+ .cp_det = { 0x2080, 8, 8, 0, 1 },
+ .dcp_det = { 0x2080, 8, 8, 0, 1 },
+ .dp_det = { 0x2080, 9, 9, 1, 0 },
+ .idm_sink_en = { 0x2010, 5, 5, 1, 0 },
+ .idp_sink_en = { 0x2010, 5, 5, 0, 1 },
+ .idp_src_en = { 0x2010, 14, 14, 0, 1 },
+ .rdm_pdwn_en = { 0x2010, 14, 14, 0, 1 },
+ .vdm_src_en = { 0x2010, 7, 6, 0, 3 },
+ .vdp_src_en = { 0x2010, 7, 6, 0, 3 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
{
.reg = 0x0,
@@ -2378,6 +2513,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
+ { .compatible = "rockchip,rk3572-usb2phy", .data = &rk3572_phy_cfgs },
{ .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
--
2.34.1
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