[PATCH 2/2] arm64: dts: rockchip: Fix GPU domain supply on NanoPi M5

[Leonard Lausen]

On the NanoPi M5, boot hangs during Panfrost initialization. Before this
fix, booting required blacklisting Panfrost on the kernel command line.
Loading Panfrost after boot reports a GPU power-domain acknowledgment
timeout:

  failed to get ack on domain 'gpu', val=0x113ff

Label the GPU power domain and connect its domain-supply to vdd_gpu_s0,
so the power-domain driver can manage the GPU rail. Keep mali-supply for
Panfrost's regulator use.

Fixes: 96cbdfdd3ac2 ("arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support")
Signed-off-by: Leonard Lausen <leonard at lausen.nl>

---
 arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 4 ++++
 arch/arm64/boot/dts/rockchip/rk3576.dtsi          | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
index 227fe6f3ec7c7..c056b3eeafed3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
@@ -791,24 +791,28 @@ rgmii_phy1: phy at 1 {
 		reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
 	};
 };
 
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie0_perstn>;
 	reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_m2_keym>;
 	status = "okay";
 };
 
+&pd_gpu {
+	domain-supply = <&vdd_gpu_s0>;
+};
+
 &pinctrl {
 	gmac {
 		gmac0_int: gmac0-int {
 			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 		gmac0_rst: gmac0-rst {
 			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 		gmac1_int: gmac1-int {
 			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 		gmac1_rst: gmac1-rst {
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index b0c0d3c8b1b14..0dd7e9ca908ed 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1075,25 +1075,25 @@ power-domain at RK3576_PD_NPU0 {
 							#power-domain-cells = <0>;
 						};
 						power-domain at RK3576_PD_NPU1 {
 							reg = <RK3576_PD_NPU1>;
 							clocks = <&cru HCLK_RKNN_ROOT>,
 								 <&cru ACLK_RKNN1>;
 							pm_qos = <&qos_npu_m1>;
 							#power-domain-cells = <0>;
 						};
 					};
 				};
 
-				power-domain at RK3576_PD_GPU {
+				pd_gpu: power-domain at RK3576_PD_GPU {
 					reg = <RK3576_PD_GPU>;
 					clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
 					pm_qos = <&qos_gpu>;
 					#power-domain-cells = <0>;
 				};
 
 				power-domain at RK3576_PD_NVM {
 					reg = <RK3576_PD_NVM>;
 					clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>;
 					pm_qos = <&qos_emmc>,
 						 <&qos_fspi0>;
 					#power-domain-cells = <1>;
-- 
2.47.3