[PATCH] PCI: dw-rockchip: Enable INTx affinity support

[Shawn Lin]

Hi Thomas

在 2026/10/19 星期一 4:04, Thomas Gleixner 写道:
> On Sun, Oct 18 2026 at 10:05, Manivannan Sadhasivam wrote:
>> On Tue, Sep 29, 2026 at 02:54:58PM +0800, Shawn Lin wrote:
>>> Leverage the interrupt redirection infrastructure to enable CPU
>>> affinity support for the legacy INTx interrupts. The INTx virqs are
>>> demultiplexed by the chained handler of the "legacy" interrupt, whose
>>> affinity cannot be changed, so affinity control for the INTx virqs is
>>> achieved by redirecting the handler to run in IRQ work context on the
>>> target CPU.
>>>
>>> Mask the INTx source in .irq_pre_redirect() before the handler is
>>> redirected: the legacy interrupt is level triggered, so an unmasked
>>> line would keep re-firing the chained interrupt until the redirected
>>> handler runs.
>>>
>>> Same approach as the DesignWare core, commit eaf290c404f7c39f2 ("PCI:
>>> dwc: Enable MSI affinity support").
>>>
>>> Test was done on RK3588 EVB1 board with an NVMe with pci=nomsi
>>> parameter. The /proc/interrupts columns are trimmed for brevity.
>>>
>>>    # cat /proc/interrupts | grep INTx
>>>    51:  137 0 0 0 0 0 0 0 INTx 0 Edge PCIe PME, nvme0q0, nvme0q1
>>>    # echo 10 > /proc/irq/51/smp_affinity
>>>    # dd if=/dev/nvme0n1p1 of=/dev/null bs=1M count=200
>>>    200+0 records in
>>>    200+0 records out
>>>    209715200 bytes (210 MB, 200 MiB) copied, 0.182021 s, 1.2 GB/s
>>>    # cat /proc/interrupts | grep INTx
>>>    51:  137 0 0 0 946 0 0 0 INTx 0 Edge PCIe PME, nvme0q0, nvme0q1
>>>
>>> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
>>
>> I'd like to get an Ack from Thomas for this patch since I'm not an irqchip
>> expert to decipher whether this patch is valid or not.
> 
> I'm happy to look at it, but I can't be bothered to fish it out from a
> mail archive. Can you please bounce me the original submission?

Sure, you can check it from:

https://lore.kernel.org/linux-pci/87y0bubws7.ffs@fw13/T/#mf0d53a0e27cb142ec0a2b09418ea2a7f04dbb321

> 
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