[PATCH v2] ARM: rockchip: smp: enable secondary rk3066a/rk3188 CPUs

[Heiko Stübner]

Hi Johan,

Am Dienstag, 13. Oktober 2026, 18:20:49 Mitteleuropäische Sommerzeit schrieb Johan Jonker via B4 Relay:
> From: Johan Jonker <jbx6244 at gmail.com>
> 
> Early Rockchip SoCs like rk3066a and rk3188 had boot loaders
> that remapped the boot ROM and the internal memory. Currently
> U-boot makes use of a common board file without remapping
> resulting in the secondary CPUs power up hanging in a wait loop.
> 
> Make the various boot loader methods work by:
> 
> * add code that disables remapping on both rk3066 and rk3188
> * change to use the same boot ROM path for all socs in rockchip_boot_secondary()
> * drop the rockchip_smp_prepare_sram() part
> 
> Signed-off-by: Johan Jonker <jbx6244 at gmail.com>

in general this seems to work on both my rk3188-rock and rk3066-marsboard,
after I did some changes:

> --- a/arch/arm/mach-rockchip/core.h
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * Copyright (c) 2013 MundoReader S.L.
> - * Author: Heiko Stuebner <heiko at sntech.de>
> - */
> -
> -extern char rockchip_secondary_trampoline;
> -extern char rockchip_secondary_trampoline_end;
> -
> -extern unsigned long rockchip_boot_fn;

that file is included rockchip.c as well, not sure why that is in there,
but this include needs to be removed too.

[...]

> diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
> index f659d894bfae..ece17e9cbaca 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c

[...]

> @@ -320,9 +279,27 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
>  	for (i = 1; i < ncores; i++)
>  		pmu_set_power_domain(0 + i, false);
>  
> +	/* Make sure that the remap function is disabled */
>  	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
> -		if (rockchip_smp_prepare_sram(node)) {
> -			of_node_put(node);
> +		unsigned int reg;
> +		int ret;
> +
> +		if (of_machine_is_compatible("rockchip,rk3066a")) {
> +			reg = RK3066_GRF_SOC_CON0;
> +			grf = syscon_regmap_lookup_by_compatible("rockchip,rk3066-grf");
> +		} else {
> +			reg = RK3188_GRF_SOC_CON0;
> +			grf = syscon_regmap_lookup_by_compatible("rockchip,rk3188-grf");
> +		}
> +
> +		if (IS_ERR(grf)) {
> +			pr_err("%s: could not find grf dt node\n", __func__);
> +			return;
> +		}
> +
> +		ret = regmap_update_bits(grf, reg, NOC_REMAP, 0);

the GRF registers use highword-masks, so this should probably be like
	ret = regmap_write(grf, reg, NOC_REMAP << 16);
enabling the NOC_REMAP bit for writing and thus having "0" written
to that bit.


Heiko