[PATCH 2/2] clk: rockchip: fix wrong PMU CLKSEL register on rv1103b

[Shawn Lin]

clk_32k and dbclk_pmu_gpio0 use RK3568_PMU_CLKSEL_CON(0), which is the
wrong SoC macro and resolves to 0x100 in the PERICRU region instead of
the RV1103B PMUCRU register at 0x70300. Reading or setting these clocks
would access an unrelated register.

Use RV1103B_PMUCLKSEL_CON(0), as already done for the XIN_RC_SRC clock
in the same file.

Fixes: 3e65e426d457 ("clk: rockchip: Add clock controller for the RV1103B")
Cc: Fabio Estevam <festevam at nabladev.com>
Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>

---

 drivers/clk/rockchip/clk-rv1103b.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rv1103b.c b/drivers/clk/rockchip/clk-rv1103b.c
index 7da1fda..aee1ba4 100644
--- a/drivers/clk/rockchip/clk-rv1103b.c
+++ b/drivers/clk/rockchip/clk-rv1103b.c
@@ -130,7 +130,7 @@ static struct rockchip_clk_branch rv1103b_clk_uart2_fracmux __initdata =
 
 static struct rockchip_clk_branch rv1103b_rcdiv_pmu_fracmux __initdata =
 	MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
-			RK3568_PMU_CLKSEL_CON(0), 0, 2, MFLAGS);
+			RV1103B_PMUCLKSEL_CON(0), 0, 2, MFLAGS);
 
 static struct rockchip_clk_branch rv1103b_clk_branches[] __initdata = {
 
@@ -373,7 +373,7 @@ static struct rockchip_clk_branch rv1103b_clk_branches[] __initdata = {
 	GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "lsclk_pmu_root", 0,
 			RV1103B_PMUCLKGATE_CON(0), 4, GFLAGS),
 	COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", dbclk_pmu_gpio0_p, 0,
-			RK3568_PMU_CLKSEL_CON(0), 3, 1, MFLAGS,
+			RV1103B_PMUCLKSEL_CON(0), 3, 1, MFLAGS,
 			RV1103B_PMUCLKGATE_CON(0), 5, GFLAGS),
 	GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_pmu_root", 0,
 			RV1103B_PMUCLKGATE_CON(2), 0, GFLAGS),
-- 
2.7.4