[PATCH 1/2] clk: rockchip: fix wrong gate register for clk_gpll_mux_to_ddr on rk3562

[Shawn Lin]

clk_gpll_mux_to_ddr uses RK3328_CLKGATE_CON(1), which is the wrong SoC
macro and points to an unrelated register (0x204) in the RK3562 CRU. As a
result enabling/disabling this clock writes the wrong register.

Use RK3562_DDR_CLKGATE_CON(0) with bit 0, matching the other DDR clocks
in the same PD_DDR section.

Fixes: f863d4cc79a7 ("clk: rockchip: Add clock controller for the RK3562")
Cc: Finley Xiao <finley.xiao at rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3562.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c
index b8858e5..07eeb82 100644
--- a/drivers/clk/rockchip/clk-rk3562.c
+++ b/drivers/clk/rockchip/clk-rk3562.c
@@ -411,7 +411,7 @@ static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = {
 
 	/* PD_DDR */
 	FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4,
-			RK3328_CLKGATE_CON(1), 6, GFLAGS),
+			RK3562_DDR_CLKGATE_CON(0), 0, GFLAGS),
 	COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL,
 			RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS,
 			RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS),
-- 
2.7.4