[PATCH 3/3] arm64: dts: rockchip: Add Axelera AI metis-sbc

[Heiko Stuebner]

Hi,

Am Freitag, 22. Mai 2026, 19:49:18 Mitteleuropäische Sommerzeit schrieb Patrick Barsanti:

[...]

> +	pcie20_avdd0v85: pcie20-avdd0v85 {

Regulator nodes should start with "regulator-", so

    pcie20_avdd0v85: regulator-pcie20-avdd0v85

same for all others.


> +		compatible = "regulator-fixed";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <850000>;
> +		regulator-max-microvolt = <850000>;
> +		regulator-name = "pcie20_avdd0v85";
> +		vin-supply = <&vdda_0v85_s0>;
> +	};



> +&cpu_b0 {
> +	cpu-supply = <&vdd_cpu_big0_s0>;
> +	mem-supply = <&vdd_cpu_big0_s0>;
> +};

There is no mem-supply in the mainline binidng, and it's the same
regulators anyway. Again, same for all cpu nodes.

You should be able to run something like

  make ARCH=arm64 .... CHECK_DTBS=y rockchip/rk3588-metis-sbc.dtb

to find all the binding problems.


> +&gmac0 {
> +	clock_in_out = "output";
> +	phy-handle = <&rgmii_phy0>;
> +	/* Use rgmii-rxid mode to disable rx delay inside Soc */

no need for that comment

> +	phy-mode = "rgmii-rxid";
> +	pinctrl-0 = <&gmac0_miim
> +		     &gmac0_tx_bus2
> +		     &gmac0_rx_bus2
> +		     &gmac0_rgmii_clk
> +		     &gmac0_rgmii_bus>;

please add a pinctrl entry (setting to GPIO) for that reset-pin
Though ... is that the phy-reset ... this should be ideally
described the phy node with its reset-gpios property.

> +	pinctrl-names = "default";
> +	tx_delay = <0x44>;
> +	snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; /* GMAC0_RST_N */
> +	snps,reset-active-low;
> +	/* Reset time is 20ms, 100ms for rtl8211f */
> +	snps,reset-delays-us = <0 20000 100000>;
> +	status = "okay";
> +};
> +


That's how far I got today :-)


Heiko