[PATCH V2 3/5] iio: imu: inv_icm42600: Add registers for icm42607

[Jonathan Cameron]

On Thu, 19 Mar 2026 13:29:39 -0500
Chris Morgan <macroalpha82 at gmail.com> wrote:

> From: Chris Morgan <macromorgan at hotmail.com>
> 
> Add the register layout for the icm_42607. Most of the registers are
> similar to that of the icm42600, though at different addresses.
> 
> Signed-off-by: Chris Morgan <macromorgan at hotmail.com>
Hi Chris,

Just taking a quick look given Jean-Baptiste's concerns
about doing this in the existing driver.

Thanks,

Jonathan

>  
> +/* ICM42607 Specific registers. */
> +
> +/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */
> +
> +/* Register Map for User Bank 0 */
> +#define INV_ICM42607_REG_DEVICE_CONFIG			0x01
> +#define INV_ICM42607_DEVICE_CONFIG_SPI_AP_4WIRE		BIT(2)
> +#define INV_ICM42607_DEVICE_CONFIG_SPI_MODE		BIT(0)
> +
> +#define INV_ICM42607_REG_SIGNAL_PATH_RESET		0x02
> +#define INV_ICM42607_SIGNAL_PATH_RESET_SOFT_RESET	BIT(4)
> +#define INV_ICM42607_SIGNAL_PATH_RESET_FIFO_FLUSH	BIT(2)
> +
> +#define INV_ICM42607_REG_DRIVE_CONFIG1			0x03
> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_DDR_MASK		GENMASK(5, 3)
> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_DDR(_rate)	\
> +FIELD_PREP(INV_ICM42607_DRIVE_CONFIG1_I3C_DDR_MASK, (_rate))

I'd indent the second line of these two line defines to make it easier to
see it's a continuation.

> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_SDR_MASK		GENMASK(2, 0)
> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_SDR(_rate)	\
> +FIELD_PREP(INV_ICM42607_DRIVE_CONFIG1_I3C_SDR_MASK, (_rate))