[PATCH v3] PCI: dw-rockchip: Enable async probe by default

[Manivannan Sadhasivam]

Hi Robin,

On Tue, Mar 10, 2026 at 01:41:56PM +0000, Robin Murphy wrote:
> Hi Mani,
> 
> On 2026-03-04 6:48 am, Manivannan Sadhasivam wrote:
> > 
> > On Thu, 26 Feb 2026 15:40:23 +0530, Anand Moon wrote:
> > > Rockchip DWC PCIe driver currently performs synchronous link training for
> > > combo PHYs (PCIe 3.0/2.0 and SATA 3.0) during boot. This process waits for
> > > the link to be fully established, adding several milliseconds to the boot
> > > sequence. To optimize boot time, this change enables asynchronous probing,
> > > allowing link establishment to proceed in the background while the kernel
> > > continues probing other devices.
> > > 
> > > [...]
> > 
> > Applied, thanks!
> > 
> > [1/1] PCI: dw-rockchip: Enable async probe by default
> >        commit: ec392abc95932838bf7e3d659d358f4df9ff5a0a
> 
> This appears to have the side-effect that calling pci_host_probe() from
> async context can effectively force async probe for the endpoint drivers
> as well, but some drivers are not OK with that, as our CI has just
> flagged up.
> 

Thanks for reporting!

> (And as for that particular warning, ISTR last time I looked into it
> another context, the opinion of the MDIO/phy maintainers seemed to be
> "don't force async probe".)
> 

This was discussed during v2 [1] and concluded that the async probe benefits
outweigh the unharmful splat from phylib. I also agree with the above conclusion
that this splat should not prevent us from enabling async probe for PCI
controller drivers. It can easily save a few 100ms during boot.

- Mani

[1] https://lore.kernel.org/linux-pci/aYHVlS1nbCMMyF04@ryzen

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