[PATCH 3/3] arm64: dts: rockchip: Add shaping nodes for rk3576
Shawn Lin
shawn.lin at rock-chips.com
Thu Mar 5 23:40:32 PST 2026
RK3576 has shaping settings which need to be saved and restored
along with the on/off of pmdomain, so add them in the rk3576.dtsi.
Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 139 +++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 53ff6bd..9c28769 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1063,6 +1063,10 @@
<&qos_npu_nsp1>,
<&qos_npu_m0ro>,
<&qos_npu_m1ro>;
+ pm_shaping = <&shaping_npu_nsp0>,
+ <&shaping_npu_nsp1>,
+ <&shaping_npu_m0ro>,
+ <&shaping_npu_m1ro>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1072,6 +1076,7 @@
clocks = <&cru HCLK_RKNN_ROOT>,
<&cru ACLK_RKNN0>;
pm_qos = <&qos_npu_m0>;
+ pm_shaping = <&shaping_npu_m0>;
#power-domain-cells = <0>;
};
power-domain at RK3576_PD_NPU1 {
@@ -1079,6 +1084,7 @@
clocks = <&cru HCLK_RKNN_ROOT>,
<&cru ACLK_RKNN1>;
pm_qos = <&qos_npu_m1>;
+ pm_shaping = <&shaping_npu_m1>;
#power-domain-cells = <0>;
};
};
@@ -1088,6 +1094,7 @@
reg = <RK3576_PD_GPU>;
clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
pm_qos = <&qos_gpu>;
+ pm_shaping = <&shaping_gpu>;
#power-domain-cells = <0>;
};
@@ -1129,6 +1136,9 @@
<&cru ACLK_MMU1>;
pm_qos = <&qos_mmu0>,
<&qos_mmu1>;
+ pm_shaping = <&shaping_mmu0>,
+ <&shaping_mmu1>;
+
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1149,6 +1159,7 @@
clocks = <&cru ACLK_VEPU1>,
<&cru HCLK_VEPU1>;
pm_qos = <&qos_vepu1>;
+ pm_shaping = <&shaping_vepu1>;
#power-domain-cells = <0>;
};
@@ -1169,6 +1180,10 @@
<&qos_rga0>,
<&qos_rga1>,
<&qos_vdpp>;
+ pm_shaping = <&shaping_rga0>,
+ <&shaping_rga1>,
+ <&shaping_jpeg>,
+ <&shaping_vdpp>;
#power-domain-cells = <0>;
};
@@ -1177,6 +1192,7 @@
clocks = <&cru ACLK_RKVDEC_ROOT>,
<&cru HCLK_RKVDEC>;
pm_qos = <&qos_rkvdec>;
+ pm_shaping = <&shaping_rkvdec>;
#power-domain-cells = <0>;
};
@@ -1199,6 +1215,11 @@
<&qos_vicap_m0>,
<&qos_vpss_mro>,
<&qos_vpss_mwo>;
+ pm_shaping = <&shaping_isp_mro>,
+ <&shaping_isp_mwo>,
+ <&shaping_vicap_m0>,
+ <&shaping_vpss_mro>,
+ <&shaping_vpss_mwo>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1208,6 +1229,7 @@
clocks = <&cru ACLK_VEPU0>,
<&cru HCLK_VEPU0>;
pm_qos = <&qos_vepu0>;
+ pm_shaping = <&shaping_vepu0>;
#power-domain-cells = <0>;
};
};
@@ -1220,6 +1242,8 @@
<&cru PCLK_VOP_ROOT>;
pm_qos = <&qos_vop_m0>,
<&qos_vop_m1ro>;
+ pm_shaping = <&shaping_vop_m0>,
+ <&shaping_vop_m1ro>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1602,11 +1626,21 @@
reg = <0x0 0x27f05000 0x0 0x20>;
};
+ shaping_gpu: shaping at 27f05088 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f05088 0x0 0x4>;
+ };
+
qos_vepu1: qos at 27f06000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f06000 0x0 0x20>;
};
+ shaping_vepu1: shaping at 27f06088 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f06088 0x0 0x4>;
+ };
+
qos_npu_mcu: qos at 27f08000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f08000 0x0 0x20>;
@@ -1622,6 +1656,16 @@
reg = <0x0 0x27f08100 0x0 0x20>;
};
+ shaping_npu_nsp0: shaping at 27f08188 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f08188 0x0 0x4>;
+ };
+
+ shaping_npu_nsp1: shaping at 27f08208 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f08208 0x0 0x4>;
+ };
+
qos_emmc: qos at 27f09000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f09000 0x0 0x20>;
@@ -1642,11 +1686,26 @@
reg = <0x0 0x27f0a080 0x0 0x20>;
};
+ shaping_mmu0: shaping at 27f0a108 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f0a108 0x0 0x4>;
+ };
+
+ shaping_mmu1: shaping at 27f0a188 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f0a188 0x0 0x4>;
+ };
+
qos_rkvdec: qos at 27f0c000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0c000 0x0 0x20>;
};
+ shaping_rkvdec: shaping at 27f0c088 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f0c088 0x0 0x4>;
+ };
+
qos_crypto: qos at 27f0d000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0d000 0x0 0x20>;
@@ -1667,6 +1726,11 @@
reg = <0x0 0x27f0f000 0x0 0x20>;
};
+ shaping_vepu0: shaping at 27f0f088 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f0f088 0x0 0x4>;
+ };
+
qos_isp_mro: qos at 27f10000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f10000 0x0 0x20>;
@@ -1692,6 +1756,31 @@
reg = <0x0 0x27f10200 0x0 0x20>;
};
+ shaping_isp_mro: shaping at 27f10288 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f10288 0x0 0x4>;
+ };
+
+ shaping_isp_mwo: shaping at 27f10308 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f10308 0x0 0x4>;
+ };
+
+ shaping_vicap_m0: shaping at 27f10388 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f10388 0x0 0x4>;
+ };
+
+ shaping_vpss_mro: shaping at 27f10408 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f10408 0x0 0x4>;
+ };
+
+ shaping_vpss_mwo: shaping at 27f10488 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f10488 0x0 0x4>;
+ };
+
qos_hdcp0: qos at 27f11000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f11000 0x0 0x20>;
@@ -1707,6 +1796,16 @@
reg = <0x0 0x27f12880 0x0 0x20>;
};
+ shaping_vop_m0: shaping at 27f12908 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f12908 0x0 0x4>;
+ };
+
+ shaping_vop_m1ro: shaping at 27f12988 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f12988 0x0 0x4>;
+ };
+
qos_ebc: qos at 27f13000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f13000 0x0 0x20>;
@@ -1732,16 +1831,46 @@
reg = <0x0 0x27f13200 0x0 0x20>;
};
+ shaping_rga0: shaping at 27f13288 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f13288 0x0 0x4>;
+ };
+
+ shaping_rga1: shaping at 27f13308 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f13308 0x0 0x4>;
+ };
+
+ shaping_jpeg: shaping at 27f13388 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f13388 0x0 0x4>;
+ };
+
+ shaping_vdpp: shaping at 27f13408 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f13408 0x0 0x4>;
+ };
+
qos_npu_m0: qos at 27f20000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f20000 0x0 0x20>;
};
+ shaping_npu_m0: shaping at 27f20088 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f20088 0x0 0x4>;
+ };
+
qos_npu_m1: qos at 27f21000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f21000 0x0 0x20>;
};
+ shaping_npu_m1: shaping at 27f21088 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f21088 0x0 0x4>;
+ };
+
qos_npu_m0ro: qos at 27f22080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f22080 0x0 0x20>;
@@ -1752,6 +1881,16 @@
reg = <0x0 0x27f22100 0x0 0x20>;
};
+ shaping_npu_m0ro: shaping at 27f22188 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f22188 0x0 0x4>;
+ };
+
+ shaping_npu_m1ro: shaping at 27f22208 {
+ compatible = "rockchip,rk3576-shaping", "syscon";
+ reg = <0x0 0x27f22208 0x0 0x4>;
+ };
+
gmac0: ethernet at 2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;
--
2.7.4
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