[PATCH] PCI: dw-rockchip: Disable BAR 0 and BAR 1 for RC mode

[Shawn Lin]

Hi Mani

在 2026/01/13 星期二 22:29, Manivannan Sadhasivam 写道:
> On Wed, Dec 24, 2025 at 06:01:01PM +0800, Shawn Lin wrote:
>> To slitence the useless bar allocation error log of RC when
>> scanning bus, as RC doesn't need BARs at all.
> 
> It is not RC, but Root Port. It is OK to disable the Root Port BARs if they
> don't serve any purpose, but I think the issue is that the BAR size is bogus.
> Both BARs report 1GiB of size, which I don't think it makes sense for a Root
> Port.
> 

Sure, it's the root port reports the bogus BARS size.

> Can I reword the commit message as:
> 
> Some Rockchip PCIe Root Port report bogus size of 1GiB for the BAR memories and
> they cause below resource allocation issue during probe. Since there is no use
> of the Root Port BAR memories, disable both of them.
> 

Looks fine to me. Would you prefer a v2 or you could amend the commit
msg while applying this patch?

Thanks.

> - Mani
> 
>>
>>    pci 0000:00:00.0: [1d87:3588] type 01 class 0x060400 PCIe Root Port
>>    pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x3fffffff]
>>    pci 0000:00:00.0: BAR 1 [mem 0x00000000-0x3fffffff]
>>    pci 0000:00:00.0: ROM [mem 0x00000000-0x0000ffff pref]
>> 	...
>>    pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned
>>    pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space
>>    pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign
>>    pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: assigned
>>    pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: releasing
>>    pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: releasing
>>    pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned
>>    pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space
>>    pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign
>>
>> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
>> ---
>>
>>   drivers/pci/controller/dwc/pcie-dw-rockchip.c | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> index f8605fe..e421fa0 100644
>> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> @@ -80,6 +80,8 @@
>>   #define  PCIE_LINKUP_MASK		GENMASK(17, 16)
>>   #define  PCIE_LTSSM_STATUS_MASK		GENMASK(5, 0)
>>   
>> +#define PCIE_TYPE0_HDR_DBI2_OFFSET      0x100000
>> +
>>   struct rockchip_pcie {
>>   	struct dw_pcie pci;
>>   	void __iomem *apb_base;
>> @@ -292,6 +294,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
>>   	if (irq < 0)
>>   		return irq;
>>   
>> +	pci->dbi_base2 = pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
>> +
>>   	ret = rockchip_pcie_init_irq_domain(rockchip);
>>   	if (ret < 0)
>>   		dev_err(dev, "failed to init irq domain\n");
>> @@ -302,6 +306,10 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
>>   	rockchip_pcie_configure_l1ss(pci);
>>   	rockchip_pcie_enable_l0s(pci);
>>   
>> +	/* Disable RC's BAR0 and BAR1 */
>> +	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
>> +	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);
>> +
>>   	return 0;
>>   }
>>   
>> -- 
>> 2.7.4
>>
>>
>