[PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support

[Bjorn Helgaas]

On Mon, Jan 12, 2026 at 09:20:00AM +0800, Shawn Lin wrote:
> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
> LTSSM history. Any LTSSM change will be recorded. It's userful
> for debug purpose, for example link failure, etc.

s/userful/useful/

> +		 * Hardware Mechanism: The ring FIFO employs two tracking counters:
> +		 * - 'last-read-point': maintains the user's last read position
> +		 * - 'last-valid-point': tracks the hardware's last state update
> +		 *
> +		 * Software Handling: When two consecutive LTSSM states are identical,
> +		 * it indicates invalid subsequent data in the FIFO. In this case, we
> +		 * skip the remaining entries. The dual-counter design ensures that on
> +		 * the next state transition, reading can resume from the last user
> +		 * position.

Wrap this to fit in 80 columns like the rest of the file.  Occasional
code lines that don't fit because of indentation or long meaningful
names are tolerable, but reading plain English text that doesn't fit
for no real reason is just annoying.