[PATCH v2 6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver
Frank Li
Frank.li at nxp.com
Wed Feb 25 12:27:46 PST 2026
On Wed, Feb 25, 2026 at 06:03:29PM +0100, Niklas Cassel wrote:
> The current EPC core design relies on an EPC driver disabling all BARs by
> default. An EPF driver will then enable the BARs that it wants to enabled.
>
> This design is there because there is no epc->ops->disable_bar().
> (There is a epc->ops->clear_bar(), but that is only to disable a BAR that
> has been enabled using epc->ops->set_bar() first.)
>
> By default, an EPF driver will not be able to get/enable BARs that are
> marked as BAR_RESERVED or BAR_DISABLED (see pci_epc_get_next_free_bar()).
>
> Since the current EPC code design requires an EPC driver to disable all
> BARs by default, let's move this to DWC common code from each glue driver.
>
> BAR_RESERVED BARs are not disabled by default because these BARs are
> hardware backed, and should only be disabled explicitly by an EPF driver
> if absolutely necessary for the EPF driver to function correctly.
> (This is similar to how e.g. NVMe may have vendor specific BARs outside of
> the mandatory BAR0 which contains the NVMe registers.)
>
> Note that there is currently no EPC operation to disable a BAR that has not
> first been programmed using pci_epc_set_bar(). If an EPF driver ever wants
> to disable a BAR marked as BAR_RESERVED, a disable_bar() operation would
> have to be added first.
>
> No functional changes intended.
>
> Tested-by: Manikanta Maddireddy <mmaddireddy at nvidia.com>
> Reviewed-by: Manikanta Maddireddy <mmaddireddy at nvidia.com>
> Signed-off-by: Niklas Cassel <cassel at kernel.org>
> ---
Reviewed-by: Frank Li <Frank.Li at nxp.com>
> drivers/pci/controller/dwc/pci-dra7xx.c | 4 ----
> drivers/pci/controller/dwc/pci-imx6.c | 10 --------
> .../pci/controller/dwc/pci-layerscape-ep.c | 4 ----
> drivers/pci/controller/dwc/pcie-artpec6.c | 4 ----
> .../pci/controller/dwc/pcie-designware-ep.c | 24 +++++++++++++++++++
> .../pci/controller/dwc/pcie-designware-plat.c | 10 --------
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 ----
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 --------
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 10 --------
> drivers/pci/controller/dwc/pcie-stm32-ep.c | 10 --------
> drivers/pci/controller/dwc/pcie-tegra194.c | 10 --------
> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 10 --------
> 12 files changed, 24 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index d5d26229063f..cd904659c321 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -378,10 +378,6 @@ static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> - enum pci_barno bar;
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
>
> dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
> }
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index ec1e3557ca53..f5fe5cfc46c7 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1401,15 +1401,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
> .stop_link = imx_pcie_stop_link,
> };
>
> -static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - enum pci_barno bar;
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -
> - for (bar = BAR_0; bar <= BAR_5; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
> static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> unsigned int type, u16 interrupt_num)
> {
> @@ -1478,7 +1469,6 @@ imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
> }
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> - .init = imx_pcie_ep_init,
> .raise_irq = imx_pcie_ep_raise_irq,
> .get_features = imx_pcie_ep_get_features,
> };
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 5a03a8f895f9..1f5fccdb4ff4 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -152,15 +152,11 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
> struct dw_pcie_ep_func *ep_func;
> - enum pci_barno bar;
>
> ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
> if (!ep_func)
> return;
>
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -
> pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
> pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
> }
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index e994b75986c3..55cb957ae1f3 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -340,15 +340,11 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
> - enum pci_barno bar;
>
> artpec6_pcie_assert_core_reset(artpec6_pcie);
> artpec6_pcie_init_phy(artpec6_pcie);
> artpec6_pcie_deassert_core_reset(artpec6_pcie);
> artpec6_pcie_wait_for_phy(artpec6_pcie);
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> }
>
> static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 295076cf70de..386bfb7b2bf6 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -1114,6 +1114,28 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
> dw_pcie_dbi_ro_wr_dis(pci);
> }
>
> +static void dw_pcie_ep_disable_bars(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + enum pci_epc_bar_type bar_type;
> + enum pci_barno bar;
> +
> + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
> + bar_type = dw_pcie_ep_get_bar_type(ep, bar);
> +
> + /*
> + * Reserved BARs should not get disabled by default. All other
> + * BAR types are disabled by default.
> + *
> + * This is in line with the current EPC core design, where all
> + * BARs are disabled by default, and then the EPF driver enables
> + * the BARs it wishes to use.
> + */
> + if (bar_type != BAR_RESERVED)
> + dw_pcie_ep_reset_bar(pci, bar);
> + }
> +}
> +
> /**
> * dw_pcie_ep_init_registers - Initialize DWC EP specific registers
> * @ep: DWC EP device
> @@ -1196,6 +1218,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
> if (ep->ops->init)
> ep->ops->init(ep);
>
> + dw_pcie_ep_disable_bars(ep);
> +
> /*
> * PCIe r6.0, section 7.9.15 states that for endpoints that support
> * PTM, this capability structure is required in exactly one
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index 8530746ec5cb..d103ab759c4e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -32,15 +32,6 @@ struct dw_plat_pcie_of_data {
> static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
> };
>
> -static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
> static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> unsigned int type, u16 interrupt_num)
> {
> @@ -73,7 +64,6 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
> }
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> - .init = dw_plat_pcie_ep_init,
> .raise_irq = dw_plat_pcie_ep_raise_irq,
> .get_features = dw_plat_pcie_get_features,
> };
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index ecc28093c589..4e9b813c3afb 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -361,13 +361,9 @@ static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
> static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
>
> rockchip_pcie_enable_l0s(pci);
> rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> };
>
> static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index e55675b3840a..e8c8ba1659fd 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -861,17 +861,7 @@ qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
> return &qcom_pcie_epc_features;
> }
>
> -static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
> -
> - for (bar = BAR_0; bar <= BAR_5; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
> static const struct dw_pcie_ep_ops pci_ep_ops = {
> - .init = qcom_pcie_ep_init,
> .raise_irq = qcom_pcie_ep_raise_irq,
> .get_features = qcom_pcie_epc_get_features,
> };
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index 9dd05bac22b9..1198ddc1752c 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -386,15 +386,6 @@ static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
> writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
> }
>
> -static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
> static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)
> {
> writel(0, rcar->base + PCIEDMAINTSTSEN);
> @@ -449,7 +440,6 @@ static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> .pre_init = rcar_gen4_pcie_ep_pre_init,
> - .init = rcar_gen4_pcie_ep_init,
> .raise_irq = rcar_gen4_pcie_ep_raise_irq,
> .get_features = rcar_gen4_pcie_ep_get_features,
> .get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
> diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c
> index c1944b40ce02..a7988dff1045 100644
> --- a/drivers/pci/controller/dwc/pcie-stm32-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c
> @@ -28,15 +28,6 @@ struct stm32_pcie {
> unsigned int perst_irq;
> };
>
> -static void stm32_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
> static int stm32_pcie_start_link(struct dw_pcie *pci)
> {
> struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
> @@ -82,7 +73,6 @@ stm32_pcie_get_features(struct dw_pcie_ep *ep)
> }
>
> static const struct dw_pcie_ep_ops stm32_pcie_ep_ops = {
> - .init = stm32_pcie_ep_init,
> .raise_irq = stm32_pcie_raise_irq,
> .get_features = stm32_pcie_get_features,
> };
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 9f9453e8cd23..3a6bffaff9ea 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1923,15 +1923,6 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
> return IRQ_HANDLED;
> }
>
> -static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
> -
> - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -};
> -
> static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
> {
> /* Tegra194 supports only INTA */
> @@ -2008,7 +1999,6 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
> }
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> - .init = tegra_pcie_ep_init,
> .raise_irq = tegra_pcie_ep_raise_irq,
> .get_features = tegra_pcie_ep_get_features,
> };
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index 5bde3ee682b5..494376d1812d 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -203,15 +203,6 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci)
> uniphier_pcie_ltssm_enable(priv, false);
> }
>
> -static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - enum pci_barno bar;
> -
> - for (bar = BAR_0; bar <= BAR_5; bar++)
> - dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
> static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -283,7 +274,6 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)
> }
>
> static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
> - .init = uniphier_pcie_ep_init,
> .raise_irq = uniphier_pcie_ep_raise_irq,
> .get_features = uniphier_pcie_get_features,
> };
> --
> 2.53.0
>
More information about the Linux-rockchip
mailing list