[PATCH v4 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support

[Steven Rostedt]

On Thu, 22 Jan 2026 10:02:20 +0800
Shawn Lin <shawn.lin at rock-chips.com> wrote:

>  
> +#ifdef CONFIG_TRACING
> +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
> +{
> +	struct rockchip_pcie *rockchip = container_of(work,
> +						struct rockchip_pcie,
> +						trace_work.work);
> +	struct dw_pcie *pci = &rockchip->pci;
> +	enum dw_pcie_ltssm state;
> +	u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
> +
> +	if (!pci_ltssm_tp_enabled())
> +		goto skip_trace;

You can use:

	if (!trace_pcie_ltssm_state_transition_enabled())
		goto skip_trace;

The above is a static branch. That means when tracing is disabled, it is
basically:

	goto skip_trace;

and when tracing is enabled it is a nop.

-- Steve


> +
> +	for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
> +		val = rockchip_pcie_readl_apb(rockchip,
> +				PCIE_CLIENT_DBG_FIFO_STATUS);
> +		rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
> +		l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
> +		val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
> +
> +		/*
> +		 * Hardware Mechanism: The ring FIFO employs two tracking
> +		 * counters:
> +		 * - 'last-read-point': maintains the user's last read position
> +		 * - 'last-valid-point': tracks the HW's last state update
> +		 *
> +		 * Software Handling: When two consecutive LTSSM states are
> +		 * identical, it indicates invalid subsequent data in the FIFO.
> +		 * In this case, we skip the remaining entries. The dual counter
> +		 * design ensures that on the next state transition, reading can
> +		 * resume from the last user position.
> +		 */
> +		if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
> +			break;
> +
> +		state = prev_val = val;
> +		if (val == DW_PCIE_LTSSM_L1_IDLE) {
> +			if (l1ss == 2)
> +				state = DW_PCIE_LTSSM_L1_2;
> +			else if (l1ss == 1)
> +				state = DW_PCIE_LTSSM_L1_1;
> +		}
> +
> +		trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> +				dw_pcie_ltssm_status_string(state),
> +				((rate + 1) > pci->max_link_speed) ?
> +				PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
> +	}
> +
> +skip_trace:
> +	schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
> +}
> +
> +static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
> +				      bool enable)
> +{
> +	if (enable) {
> +		rockchip_pcie_writel_apb(rockchip,
> +					 PCIE_CLIENT_DBG_TRANSITION_DATA,
> +					 PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0);
> +		rockchip_pcie_writel_apb(rockchip,
> +					 PCIE_CLIENT_DBG_TRANSITION_DATA,
> +					 PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1);
> +		rockchip_pcie_writel_apb(rockchip,
> +					 PCIE_CLIENT_DBG_TRANSITION_DATA,
> +					 PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0);
> +		rockchip_pcie_writel_apb(rockchip,
> +					 PCIE_CLIENT_DBG_TRANSITION_DATA,
> +					 PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1);
> +		rockchip_pcie_writel_apb(rockchip,
> +					 PCIE_CLIENT_DBG_EN,
> +					 PCIE_CLIENT_DBG_FIFO_MODE_CON);
> +
> +		INIT_DELAYED_WORK(&rockchip->trace_work,
> +				  rockchip_pcie_ltssm_trace_work);
> +		schedule_delayed_work(&rockchip->trace_work, 0);
> +	} else {
> +		rockchip_pcie_writel_apb(rockchip,
> +					 PCIE_CLIENT_DBG_DIS,
> +					 PCIE_CLIENT_DBG_FIFO_MODE_CON);
> +		cancel_delayed_work_sync(&rockchip->trace_work);
> +	}
> +}
> +#else
> +static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
> +				      bool enable)
> +{
> +}
> +#endif
> +
>  static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
>  {
>  	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
> @@ -291,6 +398,9 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
>  	 * 100us as we don't know how long should the device need to reset.
>  	 */
>  	msleep(PCIE_T_PVPERL_MS);
> +
> +	rockchip_pcie_ltssm_trace(rockchip, true);
> +
>  	gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
>  
>  	return 0;
> @@ -301,6 +411,7 @@ static void rockchip_pcie_stop_link(struct dw_pcie *pci)
>  	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
>  
>  	rockchip_pcie_disable_ltssm(rockchip);
> +	rockchip_pcie_ltssm_trace(rockchip, false);
>  }
>  
>  static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)