Problematic understanding of phy-mode in Rockchip DWMAC driver

[Chaoyi Chen]

Hi all,

On 2/17/2026 1:21 AM, Diederik de Haas wrote:
> On Mon Feb 16, 2026 at 4:00 PM CET, Russell King (Oracle) wrote:
>> On Mon, Feb 16, 2026 at 02:57:48AM +0100, Andrew Lunn wrote:
>>> On Sat, Feb 14, 2026 at 07:02:08PM +0000, Russell King (Oracle) wrote:
>>>> On Sat, Feb 14, 2026 at 05:50:15PM +0100, Andrew Lunn wrote:
>>>>> Rockchip have recently started adding support for a new version, and
>>>>> appear to of listened to what we have been saying. So it could be the
>>>>> next generation of chips get this correct.
>>>>
>>>> Have you seen any proposed code from Rockchip for their new scheme?
>>>
>>> There was a patch, including a rather odd formulae to convert register
>>> value to delay. I gave some feedback, but it has been silence
>>> afterwards.
>>
>> Searching lore's netdev archive doesn't seem to bring anything up.
> 
> https://patch.msgid.link/b25d6eb2-e105-4060-86fa-c1a06396ca92@lunn.ch/
> 

I am the author of this patch series. My understanding is that
"rgmii-id" should be adopted first, and for any delays that may
need to be introduced, they should be implemented in the PHY rather
than in the GMAC, although I did try to do so. 

Did I miss something?

-- 
Best, 
Chaoyi