[PATCH] arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy

[Jonas Karlman]

Hi,

On 2/13/2026 5:10 PM, Shawn Lin wrote:
> Hi
> 
> 在 2026/02/13 星期五 23:14, MidG971 写道:
>> The PCIe 3.0 PHY requires its power supply regulator to be enabled
>> before initialization. Without the phy-supply property, the PHY
>> driver does not ensure the regulator is enabled, causing SRAM
>> initialization to timeout with "lock failed" errors:

This is incorrect, as already mentioned the ref clock is modeled as a
regulator, and this regulator is both boot-on and always-on and should
not be referenced as the phy-supply, and the reason why I did not do it
in the initial board device tree submission.

>>
>>    phy phy-fe8c0000.phy.1: phy poweron failed --> -110
>>    rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000
>>    rockchip-pcie fe280000.pcie: phy init failed: -110

How did you manage to get this? Did you use wrong/bad boot firmware?

Please try mainline U-Boot for the ROCK 3B target, that will ensure that
both the ref clock "regulator" and the two Ethernet phys are reset
before entering Linux (or other OS) using the mainline Linux device tree
for this board.

>>
>> This results in NVMe devices in the M.2 slot not being detected.
>>
>> Add phy-supply referencing vcc3v3_pi6c_03 regulator (which controls
>> the PI6C PCIe clock generator power via GPIO0_D4) to ensure proper
>> power sequencing during PHY initialization.

As already mentioned, this is not a phy regulator so adding it as a
phy-supply does not correctly reflect the hardware.

>> Fixes: 846ef7748fa9 ("arm64: dts: rockchip: Add Radxa ROCK 3B")
>> Signed-off-by: MidG971 <midgy971 at gmail.com>
>> Co-developed-by: Claude <noreply at anthropic.com>
>> Signed-off-by: Claude <noreply at anthropic.com>
> 
> Should put your SOB at last.
> 
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> index c5f67dd6dfd9..a1b2c3d4e5f6 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> @@ -404,6 +404,7 @@ &pcie2x1 {
>>   };
>>
>>   &pcie30phy {
>> +	phy-supply = <&vcc3v3_pi6c_03>;
> 
> As a fix which need to be backported, it looks fine for just one-line
> change.

I disagree, as you mention below, and as mentioned in a comment in the
device tree, the ref clk generator is modeled as a regulator that is
boot-on and always-on that is normally enabled by boot firmware.

> However, the whole commit message is misleading. power supply for
> pcie30phy is powred up with all other phys' when booting, for instance,
> USB, otherwise all IP using PHY should not work, not just PCIe. So 
> actually it's not the power but the input refclk, and apprently pi6c
> is a 100MHz clock generator which was designed to be a regulator by
> mistake in the first place.
> 
> If you would like to clean it up later, you could use a 
> gated-fixed-clock like:

Agree, if anything please re-model the ref clk regulator as a
gated-fixed-clock instead of adding an incorrect phy-supply.

And please try mainline U-Boot targeted for you board if you intend on
using mainline Linux for your board, should most likely fix your PCIe
issue.

Regards,
Jonas

> 
> https://lore.kernel.org/linux-rockchip/35e97a41-b88b-f526-351f-d4c5f70ee4e9@rock-chips.com/T/#u
> 
> 
>>   	status = "okay";
>>   };
>>
>> --
>> 2.39.5