[PATCH] mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode

[Ulf Hansson]

On Mon, 22 Dec 2025 at 08:11, Shawn Lin <shawn.lin at rock-chips.com> wrote:
>
> When operating in HS200 or HS400 timing modes, reducing the clock frequency
> below 52MHz will lead to link broken as the Rockchip DWC MSHC controller
> requires maintaining a minimum clock of 52MHz in these modes.
>
> Add a check to prevent illegal clock reduction through debugfs:
>
> root at debian:/# echo 50000000 > /sys/kernel/debug/mmc0/clock
> root at debian:/# [   30.090146] mmc0: running CQE recovery
> mmc0: cqhci: Failed to halt
> mmc0: cqhci: spurious TCN for tag 0
> WARNING: drivers/mmc/host/cqhci-core.c:797 at cqhci_irq+0x254/0x818, CPU#1: kworker/1:0H/24
> Modules linked in:
> CPU: 1 UID: 0 PID: 24 Comm: kworker/1:0H Not tainted 6.19.0-rc1-00001-g09db0998649d-dirty #204 PREEMPT
> Hardware name: Rockchip RK3588 EVB1 V10 Board (DT)
> Workqueue: kblockd blk_mq_run_work_fn
> pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : cqhci_irq+0x254/0x818
> lr : cqhci_irq+0x254/0x818
> ...
>
> Fixes: c6f361cba51c ("mmc: sdhci-of-dwcmshc: add support for rk3588")
> Cc: Sebastian Reichel <sebastian.reichel at collabora.com>
> Cc: Yifeng Zhao <yifeng.zhao at rock-chips.com>
> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>

Applied for fixes and by adding a stable-tag, thanks!

Kind regards
Uffe


> ---
>
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 51949cd..204830b 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -739,6 +739,13 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
>         sdhci_writel(host, extra, reg);
>
>         if (clock <= 52000000) {
> +               if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
> +                   host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
> +                       dev_err(mmc_dev(host->mmc),
> +                               "Can't reduce the clock below 52MHz in HS200/HS400 mode");
> +                       return;
> +               }
> +
>                 /*
>                  * Disable DLL and reset both of sample and drive clock.
>                  * The bypass bit and start bit need to be set if DLL is not locked.
> --
> 2.7.4
>