Re: [PATCH v2 1/4] PCI:?==?utf-8?q? rockchip: limit RK3399 to 2.5 GT/s to prevent damage

[Dragan Simic]

Hello Anand,

On Wednesday, December 24, 2025 09:04 CET, Anand Moon <linux.amoon at gmail.com> wrote:
> On Wed, 24 Dec 2025 at 11:08, Geraldo Nascimento
> <geraldogabriel at gmail.com> wrote:
> > On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon at gmail.com> wrote:
> > > On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> > > <geraldogabriel at gmail.com> wrote:
> > > > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > > > from the default and drive at 2.5 GT/s only, even if the DT
> > > > max-link-speed property is invalid or inexistent.
> > > >
> > > > This change is corroborated by RK3399 official datasheet [1], which
> > > > says maximum link speed for this platform is 2.5 GT/s.
> > > >
> > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > > >
> > > To accurately determine the operating speed, we can leverage the
> > > PCIE_CLIENT_BASIC_STATUS0/1 fields.
> > > This provides a dynamic mechanism to resolve the issue.
> > >
> > > [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
> >
> > not to put you down but I think your approach adds unnecessary complexity.
> >
> > All I care really is that the Kernel Project isn't blamed in the
> > future if someone happens to lose their data.
> >
> Allow the hardware to negotiate the link speed based on the
> available number of lanes.
> I don’t anticipate any data loss, since PCIe will automatically
> configure the device speed with link training..

Please, note that this isn't about performing auto negotiation
and following its results, but about "artificially" limiting the
PCIe link speed to 2.5 GT/s on RK3399, because it's well known
by Rockchip that 5 GT/s on RK3399's PCIe interface may cause
issues and data corruption in certain corner cases.