[PATCH v3 1/3] arm64: dts: rockchip: add mipi dcphy nodes to rk3588

[Sebastian Reichel]

Hi,

On Wed, Feb 26, 2025 at 03:09:40PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner at cherry.de>
> 
> Add the two MIPI-DC-phy nodes to the RK3588, that will be used by the
> DSI2 controllers and hopefully in some future also for camera input.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner at cherry.de>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel at collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel at collabora.com> # RK3588 EVB1

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 8b497eb5da16..5535d5d905f6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -574,6 +574,16 @@ sys_grf: syscon at fd58c000 {
>  		reg = <0x0 0xfd58c000 0x0 0x1000>;
>  	};
>  
> +	mipidcphy0_grf: syscon at fd5e8000 {
> +		compatible = "rockchip,rk3588-dcphy-grf", "syscon";
> +		reg = <0x0 0xfd5e8000 0x0 0x4000>;
> +	};
> +
> +	mipidcphy1_grf: syscon at fd5ec000 {
> +		compatible = "rockchip,rk3588-dcphy-grf", "syscon";
> +		reg = <0x0 0xfd5ec000 0x0 0x4000>;
> +	};
> +
>  	vop_grf: syscon at fd5a4000 {
>  		compatible = "rockchip,rk3588-vop-grf", "syscon";
>  		reg = <0x0 0xfd5a4000 0x0 0x2000>;
> @@ -2915,6 +2925,38 @@ usbdp_phy0: phy at fed80000 {
>  		status = "disabled";
>  	};
>  
> +	mipidcphy0: phy at feda0000 {
> +		compatible = "rockchip,rk3588-mipi-dcphy";
> +		reg = <0x0 0xfeda0000 0x0 0x10000>;
> +		rockchip,grf = <&mipidcphy0_grf>;
> +		clocks = <&cru PCLK_MIPI_DCPHY0>,
> +			 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
> +		clock-names = "pclk", "ref";
> +		resets = <&cru SRST_M_MIPI_DCPHY0>,
> +			 <&cru SRST_P_MIPI_DCPHY0>,
> +			 <&cru SRST_P_MIPI_DCPHY0_GRF>,
> +			 <&cru SRST_S_MIPI_DCPHY0>;
> +		reset-names = "m_phy", "apb", "grf", "s_phy";
> +		#phy-cells = <1>;
> +		status = "disabled";
> +	};
> +
> +	mipidcphy1: phy at fedb0000 {
> +		compatible = "rockchip,rk3588-mipi-dcphy";
> +		reg = <0x0 0xfedb0000 0x0 0x10000>;
> +		rockchip,grf = <&mipidcphy1_grf>;
> +		clocks = <&cru PCLK_MIPI_DCPHY1>,
> +			 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
> +		clock-names = "pclk", "ref";
> +		resets = <&cru SRST_M_MIPI_DCPHY1>,
> +			 <&cru SRST_P_MIPI_DCPHY1>,
> +			 <&cru SRST_P_MIPI_DCPHY1_GRF>,
> +			 <&cru SRST_S_MIPI_DCPHY1>;
> +		reset-names = "m_phy", "apb", "grf", "s_phy";
> +		#phy-cells = <1>;
> +		status = "disabled";
> +	};
> +
>  	combphy0_ps: phy at fee00000 {
>  		compatible = "rockchip,rk3588-naneng-combphy";
>  		reg = <0x0 0xfee00000 0x0 0x100>;
> -- 
> 2.47.2
> 
> 
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