[PATCH v5 12/14] PCI: rockchip-ep: Improve link training

[Damien Le Moal]

On 11/16/24 08:03, Bjorn Helgaas wrote:
> On Thu, Oct 17, 2024 at 10:58:47AM +0900, Damien Le Moal wrote:
>> The Rockchip RK3399 TRM V1.3 Part2, Section 17.5.8.1.2, step 7,
>> describes the endpoint mode link training process clearly and states
>> that:
>>   Insure link training completion and success by observing link_st field
>>   in PCIe Client BASIC_STATUS1 register change to 2'b11. If both side
>>   support PCIe Gen2 speed, re-train can be Initiated by asserting the
>>   Retrain Link field in Link Control and Status Register. The software
>>   should insure the BASIC_STATUS0[negotiated_speed] changes to "1", that
>>   indicates re-train to Gen2 successfully.
> 
> Since this only adds code and doesn't change existing code, I assume
> this hardware doesn't automatically train to gen2 without this new
> software assistance?
> 
> So the effect of this change is to use gen2 speed when supported by
> both partners, when previously we only got gen1?

Yes. The host side has something similar as well.


-- 
Damien Le Moal
Western Digital Research