[PATCH] arm64: dts: rockchip: qnap-ts433: Simplify network PHY connection

[Jonas Karlman]

On 2024-03-04 16:32, Diederik de Haas wrote:
> On Monday, 4 March 2024 14:09:15 CET Andrew Lunn wrote:
>>>> Andrew already pointed out when I posted the patch introducing the gmac0
>>>> node that rgmii-id would be the preferred way to setup things. Back
>>>> then this didn't happen because this change broke reception of network
>>>> packets. However this only happend because I didn't have the right phy
>>>> driver loaded.
>>>
>>> It could be that the PHY is strapped to not use its internal RX delay.
>>> And the PHY has some weird default TX delay, so having the driver
>>> put some sensible values in is probably better.
>>
>> It could also be the bootloader putting odd values into the PHY.
>>
>> Anyway, it will work better with the correct PHY, and enable WoL
>> support.
> 
> Not sure if this is the right place or way, but here we go...
> 
> A few days ago on #debian-kernel at OFTC:
> [28.02 16:35] <ukleinek> u-boot should be out of the game
> [28.02 16:36] <diederik> I'm not so sure anymore. On Quartz64 Model A and B 
> (rk3566) I had massive packet loss and tracked it down to a change in u-boot
> [28.02 16:37] <ukleinek> diederik: sounds like the Linux network driver on 
> that machine could do something better
> [28.02 16:38] <diederik> yeah, probably
> 
> I reported this about a month ago to Jonas Karlman as I bisected the problem 
> to a change in u-boot:
> 
>> diederik at bagend:~/dev/u-boot/u-boot$ git bisect bad
>> 25f56459aebced8e4bb7d01061dcb1b765b197e2 is the first bad commit
>> commit 25f56459aebced8e4bb7d01061dcb1b765b197e2
>> Author: Jonas Karlman <jonas at kwiboo.se>
>> Date:   Sun Oct 1 19:17:21 2023 +0000
>>
>>     configs: rockchip: Enable ethernet driver on RK356x boards
>>     
>>     Enable DWC_ETH_QOS_ROCKCHIP and related PHY driver on RK356x boards that
>>     have an enabled gmac node.
> 
> I just checked and both Quartz64 Model A and B have `phy-mode = "rgmii";` and 
> set `tx_delay` and `rx_delay` to some (other) values.
> Without knowing nor understanding the details, this seem very much related?

Sorry for not getting back to you sooner, but yes I would check with
phy-mode = "rgmii-id". There is also a possible issue with rk gmac
driver in both U-Boot and linux, it always set enable tx/rx delay bit.

Please, try with following in U-Boot:

diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index fa9e513faea3..e5c320c36741 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -73,7 +73,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev,
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
 	struct rockchip_platform_data *data = pdata->priv_pdata;
-	u32 con0, con1;
+	u32 con0, con1, val;
 
 	con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
 				 RK3568_GRF_GMAC0_CON0;
@@ -84,10 +84,12 @@ static int rk3568_set_to_rgmii(struct udevice *dev,
 		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
 		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
 
-	regmap_write(data->grf, con1,
-		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
-		     RK3568_GMAC_RXCLK_DLY_ENABLE |
-		     RK3568_GMAC_TXCLK_DLY_ENABLE);
+	val = RK3568_GMAC_PHY_INTF_SEL_RGMII;
+	if (rx_delay > 0)
+		val |= RK3568_GMAC_RXCLK_DLY_ENABLE;
+	if (tx_delay > 0)
+		val |= RK3568_GMAC_TXCLK_DLY_ENABLE;
+	regmap_write(data->grf, con1, val);
 
 	return 0;
 }


Also check with the series "phy: rockchip-inno-usb2: Write to correct
GRF" [1]. Trying to configure bits intended for USBGRF in GRF is
probably not that good :-)

[1] https://patchwork.ozlabs.org/cover/1903987/

Regards,
Jonas

> 
> Cheers,
>   Diederik