[PATCH v1] arm64: dts: rockchip: Add cache information to the Rockchip RK3566 and RK3568 SoC

[Dragan Simic]

On 2024-02-27 13:49, Anand Moon wrote:
> On Tue, 27 Feb 2024 at 00:39, Dragan Simic <dsimic at manjaro.org> wrote:
>> On 2024-02-26 19:23, Anand Moon wrote:
>> > As per RK3568 Datasheet and TRM add missing cache information to
>> > the Rockchip RK3566 and RK3568 SoC.
>> >
>> > - Each Cortex-A55 core has 32KB of L1 instruction cache available and
>> >       32KB of L1 data cache available with ECC.
>> > - Along with 512KB Unified L3 cache with ECC.
>> >
>> > With adding instruction cache and data cache and a write buffer to
>> > reduce the effect of main memory bandwidth and latency on data
>> > access performance.
>> >
>> > Signed-off-by: Anand Moon <linux.amoon at gmail.com>
>> 
>> I was about to send my own patch that adds the same missing cache
>> information, so please allow me to describe the proposed way to move
>> forward.
>> 
>> The way I see it, your commit summary and description need a rather
>> complete rewrite, to be more readable, more accurate, and to avoid
>> including an irrelevant (and slightly misleading) description of the
>> general role of caches.
>> 
>> Also, the changes to the dtsi file would benefit from small touch-ups
>> here and there, for improved consistency, etc.
>> 
>> With all that in mind, I propose that you withdraw your patch and let
>> me send my patch that will addresses all these issues, of course with
>> a proper tag that lists you as a co-developer.  I think that would
>> save us a fair amount of time going back and forth.
>> 
>> I hope you agree.
> 
> I have no issue with this,.If you have a better version plz share this.

Thank you, I'll send my patch within the next couple of days.