[PATCH] arm64: dts: rockchip: add missing mandatory rk3588 PCIe atu property
Sebastian Reichel
sebastian.reichel at collabora.com
Fri Oct 20 14:23:57 PDT 2023
Hello Niklas,
On Fri, Oct 20, 2023 at 02:52:20PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel at wdc.com>
>
> From the snps,dw-pcie.yaml devicetree binding:
> "At least DBI reg-space and peripheral devices CFG-space outbound window
> are required for the normal controller work. iATU memory IO region is
> also required if the space is unrolled (IP-core version >= 4.80a)."
>
> All the PCIe controllers in rk3588 are using the iATU unroll feature,
> and thus have to supply the atu property in the device tree node.
>
> The size of the iATU region equals to:
> MAX(num inbound ATU regions, num outbound ATU regions) * 0x200.
>
> Where for each 0x200 region, the registers controlling the
> IATU_REGION_OUTBOUND starts at offset 0x0, and the registers controlling
> IATU_REGION_INBOUND starts at offset 0x100.
>
> pcie3x4 and pcie3x2 have 16 ATU inbound regions, 16 ATU outbound regions,
> so they have size: max(16, 16) * 0x200 = 0x2000
>
> pcie2x1l0, pcie2x1l1, and pcie2x1l2 have 8 ATU inbound regions, 8 ATU
> outbound regions, so they have size: max(8, 8) * 0x200 = 0x1000
>
> On the rk3588 based rock-5b board:
> Before this patch, dw_pcie_iatu_detect() fails to detect all iATUs:
> rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
> rockchip-dw-pcie a41000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
> rockchip-dw-pcie a40800000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
>
> After this patch, dw_pcie_iatu_detect() succeeds to detect all iATUs:
> rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G
> rockchip-dw-pcie a41000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
> rockchip-dw-pcie a40800000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
>
> Fixes: 8d81b77f4c49 ("arm64: dts: rockchip: add rk3588 PCIe2 support")
> Fixes: 0acf4fa7f187 ("arm64: dts: rockchip: add PCIe3 support for rk3588")
> Signed-off-by: Niklas Cassel <niklas.cassel at wdc.com>
> ---
Thanks for your patch. This looks sensible, but I have two comments:
1. You need to update the Rockchip DT binding. It currently enforces that regnames
must be "dbi", "apb", "config". Thus 'make CHECK_DTBS=y rockchip/rk3588-rock-5b.dtb'
will introduce new errors after this patch is applied.
2. You calculated the exact ATU size and used that, but the binding specifies,
"iATU/eDMA registers common for all device functions. [...] Note iATU is normally
mapped to the 0x0 address of this region, while eDMA is available at 0x80000 base
address.". So the size should be big enough to include the DMA section. So I would
expect it to be 0x100000 for all controllers.
Greetings,
-- Sebastian
> arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++---------
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 ++++++++------
> 2 files changed, 20 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 5519c1430cb7..d7998a9c0c43 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -119,10 +119,11 @@ pcie3x4: pcie at fe150000 {
> ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
> <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
> - reg = <0xa 0x40000000 0x0 0x00400000>,
> + reg = <0xa 0x40000000 0x0 0x00300000>,
> <0x0 0xfe150000 0x0 0x00010000>,
> - <0x0 0xf0000000 0x0 0x00100000>;
> - reg-names = "dbi", "apb", "config";
> + <0x0 0xf0000000 0x0 0x00100000>,
> + <0xa 0x40300000 0x0 0x00002000>;
> + reg-names = "dbi", "apb", "config", "atu";
> resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> reset-names = "pwr", "pipe";
> status = "disabled";
> @@ -170,10 +171,11 @@ pcie3x2: pcie at fe160000 {
> ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
> <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
> - reg = <0xa 0x40400000 0x0 0x00400000>,
> + reg = <0xa 0x40400000 0x0 0x00300000>,
> <0x0 0xfe160000 0x0 0x00010000>,
> - <0x0 0xf1000000 0x0 0x00100000>;
> - reg-names = "dbi", "apb", "config";
> + <0x0 0xf1000000 0x0 0x00100000>,
> + <0xa 0x40700000 0x0 0x00002000>;
> + reg-names = "dbi", "apb", "config", "atu";
> resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> reset-names = "pwr", "pipe";
> status = "disabled";
> @@ -219,10 +221,11 @@ pcie2x1l0: pcie at fe170000 {
> ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
> <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
> - reg = <0xa 0x40800000 0x0 0x00400000>,
> + reg = <0xa 0x40800000 0x0 0x00300000>,
> <0x0 0xfe170000 0x0 0x00010000>,
> - <0x0 0xf2000000 0x0 0x00100000>;
> - reg-names = "dbi", "apb", "config";
> + <0x0 0xf2000000 0x0 0x00100000>,
> + <0xa 0x40b00000 0x0 0x00001000>;
> + reg-names = "dbi", "apb", "config", "atu";
> resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
> reset-names = "pwr", "pipe";
> #address-cells = <3>;
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 5544f66c6ff4..286d7b10b9dd 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -1259,10 +1259,11 @@ pcie2x1l1: pcie at fe180000 {
> ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
> <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
> - reg = <0xa 0x40c00000 0x0 0x00400000>,
> + reg = <0xa 0x40c00000 0x0 0x00300000>,
> <0x0 0xfe180000 0x0 0x00010000>,
> - <0x0 0xf3000000 0x0 0x00100000>;
> - reg-names = "dbi", "apb", "config";
> + <0x0 0xf3000000 0x0 0x00100000>,
> + <0xa 0x40f00000 0x0 0x00001000>;
> + reg-names = "dbi", "apb", "config", "atu";
> resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
> reset-names = "pwr", "pipe";
> #address-cells = <3>;
> @@ -1310,10 +1311,11 @@ pcie2x1l2: pcie at fe190000 {
> ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
> <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
> - reg = <0xa 0x41000000 0x0 0x00400000>,
> + reg = <0xa 0x41000000 0x0 0x00300000>,
> <0x0 0xfe190000 0x0 0x00010000>,
> - <0x0 0xf4000000 0x0 0x00100000>;
> - reg-names = "dbi", "apb", "config";
> + <0x0 0xf4000000 0x0 0x00100000>,
> + <0xa 0x41300000 0x0 0x00001000>;
> + reg-names = "dbi", "apb", "config", "atu";
> resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
> reset-names = "pwr", "pipe";
> #address-cells = <3>;
> --
> 2.41.0
>
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