[PATCH v2 8/8] arm64: dts: rockchip: Add rk3588 OTP node

[Cristian Ciocaltea]

Add DT node for Rockchip RK3588/RK3588S OTP memory.

Co-developed-by: Finley Xiao <finley.xiao at rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao at rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
Tested-by: Vincent Legoll <vincent.legoll at gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 767084a1ec43..d842988af418 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1822,6 +1822,60 @@ spi4: spi at fecb0000 {
 		status = "disabled";
 	};
 
+	otp: efuse at fecc0000 {
+		compatible = "rockchip,rk3588-otp";
+		reg = <0x0 0xfecc0000 0x0 0x400>;
+		clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+			 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
+		clock-names = "otp", "apb_pclk", "phy", "arb";
+		resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+			 <&cru SRST_OTPC_ARB>;
+		reset-names = "otp", "apb", "arb";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpu_code: cpu-code at 2 {
+			reg = <0x02 0x2>;
+		};
+
+		otp_id: id at 7 {
+			reg = <0x07 0x10>;
+		};
+
+		otp_cpu_version: cpu-version at 1c {
+			reg = <0x1c 0x1>;
+			bits = <3 3>;
+		};
+
+		cpub0_leakage: cpu-leakage at 17 {
+			reg = <0x17 0x1>;
+		};
+
+		cpub1_leakage: cpu-leakage at 18 {
+			reg = <0x18 0x1>;
+		};
+
+		cpul_leakage: cpu-leakage at 19 {
+			reg = <0x19 0x1>;
+		};
+
+		log_leakage: log-leakage at 1a {
+			reg = <0x1a 0x1>;
+		};
+
+		gpu_leakage: gpu-leakage at 1b {
+			reg = <0x1b 0x1>;
+		};
+
+		npu_leakage: npu-leakage at 28 {
+			reg = <0x28 0x1>;
+		};
+
+		codec_leakage: codec-leakage at 29 {
+			reg = <0x29 0x1>;
+		};
+	};
+
 	dmac2: dma-controller at fed10000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0x0 0xfed10000 0x0 0x4000>;
-- 
2.40.0