[PATCH 2/2] media: verisilicon: change confusingly named relaxed register access

[Arnd Bergmann]

On Mon, Jun 19, 2023, at 16:41, Nicolas Dufresne wrote:
> Le vendredi 16 juin 2023 à 16:48 +0200, Arnd Bergmann a écrit :
>> From: Arnd Bergmann <arnd at arndb.de>
>> 
>> The register abstraction has wrappers around both the normal writel()
>> and its writel_relaxed() counterpart, but this has led to a lot of users
>> ending up with the relaxed version.
>> 
>> There is sometimes a need to intentionally pick the relaxed accessor for
>> performance critical functions, but I noticed that each hantro_reg_write()
>> call also contains a non-relaxed readl(), which is typically much more
>> expensive than a writel, so there is little benefit here but an added
>> risk of missing a serialization against DMA.
>> 
>> To make this behave like other interfaces, use the normal accessor by
>> default and only provide the relaxed version as an alternative for
>> performance critical code. hantro_postproc.c is the only place that
>> used both the relaxed and normal writel, but this does not seem
>> cricital either, so change it all to the normal ones.
>
> In this text you spoke about potential performance side effects of existing code
> and your changes, but its left all very vague and theoretical. Have you done any
> measurement ? Do you need help with the manner ?

I don't have this hardware and have not done any measurements.
Obviously the only point of using relaxed accessors is to
improve performance in critical code paths, but from the way they
are used here it seems that this was instead just an accident
and nobody else did any comparisons either.

My guess would be that if one wanted to speed up the register
access, a better way would be to use a regmap cache to avoid
reading registers when the contents are already known.

     Arnd