[linux-next-v2 5/5] arm64: dts: rockchip: Add missing of ethernet-phy-id to reset the phy on Rock 3A SBC

[Michael Riesch]

Hi Anand,

On 11/16/22 21:01, Anand Moon wrote:
> Add MDIO description with ethernet-phy-id compatible string
> which enable calling reset of the phy. The PHY will then be probed,
> independent of if it can be found on the bus or not,
> and that probing will enable the GPIO.
> 
> ethernet-phy-id is read from ethenet register dump reg2 and reg3.
> 
> Fix following warning.
> [   12.323417] rk_gmac-dwmac fe010000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
> [   12.324078] rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1
> [   12.324099] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19)

Without this patch, the phy on my ROCK3A is properly detected:

[    1.494963] rk_gmac-dwmac fe010000.ethernet eth0: PHY [stmmac-0:00]
driver [RTL8211F Gigabit Ethernet)

but with the patch applied, only a generic phy is recognized:

[    1.398674] rk_gmac-dwmac fe010000.ethernet eth0: PHY [stmmac-0:00]
driver [Generic PHY] (irq=POLL)

This does not seem right at all. NACK to this patch!

Best regards,
Michael

> 
> Signed-off-by: Anand Moon <linux.amoon at gmail.com>
> ---
> V2: new to the patch series.
> 
> alarm at rock-3a:~$ sudo ethtool -d eth0
> [sudo] password for alarm:
> ST GMAC Registers
> GMAC Registers
> Reg0  0x08072203
> Reg1  0x00000000
> Reg2  0x00000404
> Reg3  0x00000000
> Reg4  0x00000002
> ---
>  arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> index 9f84a23a8789..fe36156a5017 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> @@ -585,7 +585,7 @@ &i2s2_2ch {
>  
>  &mdio1 {
>  	rgmii_phy1: ethernet-phy at 0 {
> -		compatible = "ethernet-phy-ieee802.3-c22";
> +		compatible = "ethernet-phy-id0000.0404", "ethernet-phy-ieee802.3-c22";
>  		reg = <0x0>;
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&eth_phy_rst>, <&eth_phy_int>;