[PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties

[Rob Herring]

On Fri, Jan 07, 2022 at 03:53:14PM -0800, Brian Norris wrote:
> DDR DVFS tuning has found that several power-saving features don't have
> good tradeoffs at higher frequencies -- at higher frequencies, we'll see
> glitches or other errors. Provide tuning controls so these can be
> disabled at higher OPPs, and left active only at the lower ones.
> 
> Signed-off-by: Brian Norris <briannorris at chromium.org>
> ---
> 
>  .../bindings/devfreq/rk3399_dmc.yaml          | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> index 2c871c57fd97..357d07c5a3df 100644
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> @@ -271,6 +271,43 @@ properties:
>        When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
>        strength. Default value is 60.
>  
> +  rockchip,pd_idle_dis_freq:

s/_/-/

on all the new properties.

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Defines the power-down idle disable frequency in Hz. When the DDR
> +      frequency is greater than pd_idle_dis_freq, power-down idle is disabled.
> +      See also rockchip,pd_idle.
> +
> +  rockchip,sr_idle_dis_freq:

'-hz' suffix. Let's not repeat the same problem.


> +    $ref: /schemas/types.yaml#/definitions/uint32

And then the type can be dropped.

> +    description:
> +      Defines the self-refresh idle disable frequency in Hz. When the DDR
> +      frequency is greater than sr_idle_dis_freq, self-refresh idle is
> +      disabled. See also rockchip,sr_idle.
> +
> +  rockchip,sr_mc_gate_idle_dis_freq:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Defines the self-refresh and memory-controller clock gating disable
> +      frequency in Hz. When the DDR frequency is greater than
> +      sr_mc_gate_idle_dis_freq, the clock will not be gated when idle. See also
> +      rockchip,sr_mc_gate_idle.
> +
> +  rockchip,srpd_lite_idle_dis_freq:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Defines the self-refresh power down idle disable frequency in Hz. When
> +      the DDR frequency is greater than srpd_lite_idle_dis_freq, memory will
> +      not be placed into self-refresh power down mode when idle. See also
> +      rockchip,srpd_lite_idle.
> +
> +  rockchip,standby_idle_dis_freq:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Defines the standby idle disable frequency in Hz. When the DDR frequency
> +      is greater than standby_idle_dis_freq, standby idle is disabled. See also
> +      rockchip,standby_idle.
> +
>  additionalProperties: false
>  
>  examples:
> @@ -294,4 +331,9 @@ examples:
>        rockchip,ddr3_odt_dis_freq = <333000000>;
>        rockchip,lpddr3_odt_dis_freq = <333000000>;
>        rockchip,lpddr4_odt_dis_freq = <333000000>;
> +      rockchip,pd_idle_dis_freq = <1000000000>;
> +      rockchip,sr_idle_dis_freq = <1000000000>;
> +      rockchip,sr_mc_gate_idle_dis_freq = <1000000000>;
> +      rockchip,srpd_lite_idle_dis_freq = <0>;
> +      rockchip,standby_idle_dis_freq = <928000000>;
>      };
> -- 
> 2.34.1.575.g55b058a8bb-goog
> 
>