[PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
Lucas Stach
l.stach at pengutronix.de
Tue Apr 26 03:40:42 PDT 2022
Am Dienstag, dem 26.04.2022 um 12:28 +0200 schrieb Martin Kepplinger:
> Am Montag, dem 25.04.2022 um 10:47 -0500 schrieb Adam Ford:
> > On Mon, Apr 25, 2022 at 10:34 AM Lucas Stach <l.stach at pengutronix.de>
> > wrote:
> > >
> > > Hi Martin,
> > >
> > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > update
> > > > > the device tree to allow both to operate. This requires the
> > > > > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
> > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > fuses, the clock-parents and clock-rates for the various VPU's
> > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > parented
> > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > >
> > > > > Signed-off-by: Adam Ford <aford173 at gmail.com>
> > > > > Reported-by: kernel test robot <lkp at intel.com>
> > > > > Reviewed-by: Ezequiel Garcia <ezequiel at vanguardiasur.com.ar>
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain at 5 {
> > > > > pgc_vpu: power-domain at 6
> > > > > {
> > > > > #power-domain-
> > > > > cells =
> > > > > <0>;
> > > > > reg =
> > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > - clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > + clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > + <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > + <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > + assigned-clocks
> > > > > =
> > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > +
> > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > +
> > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > +
> > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > + assigned-clock-
> > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +
> > > > > <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +
> > > > > <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > +
> > > > > <&clk IMX8MQ_VPU_PLL>;
> > > > > + assigned-clock-
> > > > > rates
> > > > > = <600000000>,
> > > > > +
> > > > > <600000000>,
> > > > > +
> > > > > <800000000>,
> > > > > +
> > > > > <0>;
> > > > > };
> > > > >
> > > > > pgc_disp: power-
> > > > > domain at 7 {
> > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy at 382f0040 {
> > > > > status = "disabled";
> > > > > };
> > > > >
> > > > > - vpu: video-codec at 38300000 {
> > > > > - compatible = "nxp,imx8mq-vpu";
> > > > > - reg = <0x38300000 0x10000>,
> > > > > - <0x38310000 0x10000>,
> > > > > - <0x38320000 0x10000>;
> > > > > - reg-names = "g1", "g2", "ctrl";
> > > > > - interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > - <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > - interrupt-names = "g1", "g2";
> > > > > + vpu_g1: video-codec at 38300000 {
> > > > > + compatible = "nxp,imx8mq-vpu-g1";
> > > > > + reg = <0x38300000 0x10000>;
> > > > > + interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > + power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > + };
> > > > > +
> > > > > + vpu_g2: video-codec at 38310000 {
> > > > > + compatible = "nxp,imx8mq-vpu-g2";
> > > > > + reg = <0x38310000 0x10000>;
> > > > > + interrupts = <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > + power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > + };
> > > > > +
> > > > > + vpu_blk_ctrl: blk-ctrl at 38320000 {
> > > > > + compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > > > + reg = <0x38320000 0x100>;
> > > > > + power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > > > <&pgc_vpu>;
> > > > > + power-domain-names = "bus", "g1", "g2";
> > > > > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > - <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > - clock-names = "g1", "g2", "bus";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > - <&clk
> > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > - <&clk
> > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > - <&clk
> > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > - assigned-clock-parents = <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > - <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > - <&clk
> > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > - <&clk
> > > > > IMX8MQ_VPU_PLL>;
> > > > > - assigned-clock-rates = <600000000>,
> > > > > <600000000>,
> > > > > - <800000000>,
> > > > > <0>;
> > > > > - power-domains = <&pgc_vpu>;
> > > > > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > + clock-names = "g1", "g2";
> > > > > + #power-domain-cells = <1>;
> > > > > };
> > > > >
> > > > > pcie0: pcie at 33800000 {
> > > >
> > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > >
> > > > buck4: failed to disable: -ETIMEDOUT
> > > >
> > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > to
> > > > suspend (and resuming) fails.
> > > >
> > > > Have you tested system suspend after the imx8m-blk-ctrl update on
> > > > imx8mq?
> > >
> > > I haven't tested system suspend, don't know if anyone else did.
> > > However
> > > I guess that this is just uncovering a preexisting issue in the
> > > system
> > > suspend sequencing, which you would also hit if the video decoders
> > > were
> > > active at system suspend time.
> >
> > I have not tested it either.
> >
> > >
> > > My guess is that the regulator disable fails, due to the power
> > > domains
> > > being disabled quite late in the suspend sequence, where i2c
> > > communication with the PMIC is no longer possible due to i2c being
> > > suspended already or something like that. Maybe you can dig in a
> > > bit on
> > > the actual sequence on your system and we can see how we can rework
> > > things to suspend the power domains at a time where communication
> > > with
> > > the PMIC is still possible?
> >
> > In the meantime, should we mark the regulator with regulator-always-
> > on
> > so it doesn't attempt to power it down? It might not be ideal,but it
> > might be enough to let it suspend.
> >
>
> it would be a temporary workaround, but I want to remind you that it
> wouldn't help much: even if suspending "works" again, system resume is
> broken on imx8mq since
> https://lore.kernel.org/all/a20ecd639f8e8b7fa4a9bed7a8e9590225262784.camel@puri.sm/
>
> Of course I did the current tests on v5.18-rc4 without any gpcv2
> changes to mainline. But for resume to work I need the one revert from
> the above link (plus a minor additional hack) already.
>
> If we'd have that working in mainline I could make sure it stays that
> way :)
>
This looks like the same underlying issue to me. We need to suspend the
power domains before i2c (or whatever is causing the regulator disable
fail) and only resume them after this subsystem is resumed.
Regards,
Lucas
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