[PATCH v1 6/8] spi: rockchip: Set rx_fifo interrupt waterline base on transfer item

[Mark Brown]

On Fri, Apr 23, 2021 at 04:47:48PM +0800, Jon Lin wrote:
> The error here is to calculate the width as 8 bits. In fact, 16 bits
> should be considered.

Bugfix patches like this should go at the start of a series so they can
be sent as fixes without any dependencies on earlier patches.
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