[PATCH v2 2/3] arm64: dts: rockchip: add cdn-dp node for rk3399.

[Enric Balletbo i Serra]

From: Chris Zhong <zyw at rock-chips.com>

Add a node for the cdn DP controller which is embedded in the rk3399
SoC.

Signed-off-by: Chris Zhong <zyw at rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo at collabora.com>
---
Changes since v1:
- None

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 50 ++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index cdf733e4a450..17a9dc5591c5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -457,6 +457,46 @@
 		};
 	};
 
+        cdn_dp: dp at fec00000 {
+                compatible = "rockchip,rk3399-cdn-dp";
+                reg = <0x0 0xfec00000 0x0 0x100000>;
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+                         <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+                clock-names = "core-clk", "pclk", "spdif", "grf";
+                assigned-clocks = <&cru SCLK_DP_CORE>;
+                assigned-clock-rates = <100000000>;
+                power-domains = <&power RK3399_PD_HDCP>;
+                phys = <&tcphy0_dp>, <&tcphy1_dp>;
+                resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+                         <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+                reset-names = "spdif", "dptx", "apb", "core";
+                rockchip,grf = <&grf>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                #sound-dai-cells = <1>;
+                status = "disabled";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        dp_in: port {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                dp_in_vopb: endpoint at 0 {
+                                        reg = <0>;
+                                        remote-endpoint = <&vopb_out_dp>;
+                                };
+
+                                dp_in_vopl: endpoint at 1 {
+                                        reg = <1>;
+                                        remote-endpoint = <&vopl_out_dp>;
+                                };
+                        };
+                };
+        };
+
 	gic: interrupt-controller at fee00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <4>;
@@ -1553,6 +1593,11 @@
 				reg = <3>;
 				remote-endpoint = <&mipi1_in_vopl>;
 			};
+
+                        vopl_out_dp: endpoint at 4 {
+                                reg = <4>;
+                                remote-endpoint = <&dp_in_vopl>;
+                        };
 		};
 	};
 
@@ -1605,6 +1650,11 @@
 				reg = <3>;
 				remote-endpoint = <&mipi1_in_vopb>;
 			};
+
+                        vopb_out_dp: endpoint at 4 {
+                                reg = <4>;
+                                remote-endpoint = <&dp_in_vopb>;
+                        };
 		};
 	};
 
-- 
2.15.1