[PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller

[Rob Herring]

On Wed, Dec 09, 2015 at 05:04:09PM +0800, Jeffy Chen wrote:
> Add the devicetree binding for the cru on the rk3228 which quite similar
> structured as previous clock controllers.
> 
> Signed-off-by: Jeffy Chen <jeffy.chen at rock-chips.com>

Seems like there is a lot of duplication across Rockchip cru bindings. 
Perhaps they should be combined? Otherwise:

Acked-by: Rob Herring <robh at kernel.org>

> ---
> 
>  .../bindings/clock/rockchip,rk3228-cru.txt         | 58 ++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
> new file mode 100644
> index 0000000..f323048
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
> @@ -0,0 +1,58 @@
> +* Rockchip RK3228 Clock and Reset Unit
> +
> +The RK3228 clock controller generates and supplies clock to various
> +controllers within the SoC and also implements a reset controller for SoC
> +peripherals.
> +
> +Required Properties:
> +
> +- compatible: should be "rockchip,rk3228-cru"
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +- #clock-cells: should be 1.
> +- #reset-cells: should be 1.
> +
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> +  If missing pll rates are not changeable, due to the missing pll lock status.
> +
> +Each clock is assigned an identifier and client nodes can use this identifier
> +to specify the clock which they consume. All available clocks are defined as
> +preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
> +used in device tree sources. Similar macros exist for the reset sources in
> +these files.
> +
> +External clocks:
> +
> +There are several clocks that are generated outside the SoC. It is expected
> +that they are defined using standard clock bindings with following
> +clock-output-names:
> + - "xin24m" - crystal input - required,
> + - "ext_i2s" - external I2S clock - optional,
> + - "ext_gmac" - external GMAC clock - optional
> + - "ext_hsadc" - external HSADC clock - optional
> + - "phy_50m_out" - output clock of the pll in the mac phy
> +
> +Example: Clock controller node:
> +
> +	cru: cru at 20000000 {
> +		compatible = "rockchip,rk3228-cru";
> +		reg = <0x20000000 0x1000>;
> +		rockchip,grf = <&grf>;
> +
> +		#clock-cells = <1>;
> +		#reset-cells = <1>;
> +	};
> +
> +Example: UART controller node that consumes the clock generated by the clock
> +  controller:
> +
> +	uart0: serial at 10110000 {
> +		compatible = "snps,dw-apb-uart";
> +		reg = <0x10110000 0x100>;
> +		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> +		reg-shift = <2>;
> +		reg-io-width = <4>;
> +		clocks = <&cru SCLK_UART0>;
> +	};
> -- 
> 2.1.4
> 
> 
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