[PATCH v5 06/23] clk: starfive: Add JHB100 System-0 clock generator driver
Changhuang Liang
changhuang.liang at starfivetech.com
Wed Sep 30 05:43:00 PDT 2026
Add support for JHB100 System-0 clock generator (SYS0CRG).
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
MAINTAINERS | 7 +
drivers/clk/starfive/Kconfig | 10 ++
drivers/clk/starfive/Makefile | 2 +
.../clk/starfive/clk-starfive-jhb100-sys0.c | 150 ++++++++++++++++++
4 files changed, 169 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
diff --git a/MAINTAINERS b/MAINTAINERS
index c9f542965ec5..d22078bcf488 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26217,6 +26217,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
+STARFIVE JHB100 CLOCK DRIVERS
+M: Changhuang Liang <changhuang.liang at starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/clock/starfive,jhb1*.yaml
+F: drivers/clk/starfive/clk-starfive-jhb1*
+F: include/dt-bindings/clock/starfive,jhb1*.h
+
STARFIVE JHB100 DEVICETREES
M: Changhuang Liang <changhuang.liang at starfivetech.com>
L: linux-riscv at lists.infradead.org
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 51716655554f..cd5b7754403e 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -72,3 +72,13 @@ config CLK_STARFIVE_JH7110_VOUT
help
Say yes here to support the Video-Output clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JHB100_SYS0
+ bool "StarFive JHB100 system-0 clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JHB100 if RESET_CONTROLLER
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-0 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 199ac0f37a2f..d2ba83d7d02c 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
+
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys0.c b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
new file mode 100644
index 000000000000..498afb787311
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-0 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang at starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jh71x0.h"
+
+#define JHB100_SYS0CLK_NUM_CLKS (JHB100_SYS0CLK_GPU1_NCNOC_INIT + 1)
+
+/* external clocks */
+#define JHB100_SYS0CLK_OSC (JHB100_SYS0CLK_NUM_CLKS + 0)
+#define JHB100_SYS0CLK_PLL0 (JHB100_SYS0CLK_NUM_CLKS + 1)
+#define JHB100_SYS0CLK_PLL1 (JHB100_SYS0CLK_NUM_CLKS + 2)
+#define JHB100_SYS0CLK_PLL2 (JHB100_SYS0CLK_NUM_CLKS + 3)
+
+static const char * const jhb100_sys0_ext_clk[] = {
+ "osc",
+ "pll0",
+ "pll1",
+ "pll2",
+};
+
+static const struct jh71x0_clk_data jhb100_sys0crg_clk_data[] = {
+ /* bmcpcierp */
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN, "bmcpcierp_ncnoc_main", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG, "bmcpcierp_ncnoc_cfg", 12,
+ JHB100_SYS0CLK_PLL1),
+ JH71X0__DIV(JHB100_SYS0CLK_PCIE_REF_CML, "pcie_ref_cml", 24,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT, "bmcpcierp_ncnoc_data_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN),
+ JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT, "bmcpcierp_ncnoc_cfg_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG),
+ JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG, "bmcpcierp_ncnoc_targ",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN),
+ JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_PCU, "bmcpcierp_pcu",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_OSC),
+ /* hostss0 */
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTSS0_NCNOC_CFG, "hostss0_ncnoc_cfg", 12,
+ JHB100_SYS0CLK_PLL1),
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTSS0_NCNOC_DATA, "hostss0_ncnoc_data", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400, "hostss0_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_GPIO_ESPI0_EXT, "gpio_espi0_ext", 14,
+ JHB100_SYS0CLK_PLL2),
+ /* bmcusb */
+ JH71X0__DIV(JHB100_SYS0CLK_BMCUSB_NCNOC_INIT, "bmcusb_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCUSB_NCNOC_TARG, "bmcusb_ncnoc_targ", 6,
+ JHB100_SYS0CLK_PLL1),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCUSB_SCANCLK, "bmcusb_scanclk", 5,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0_GATE(JHB100_SYS0CLK_BMCUSB_480M_SCANCLK, "bmcusb_480m_scanclk",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCUSB_SCANCLK),
+ /* vce */
+ JH71X0__DIV(JHB100_SYS0CLK_VCE_NCNOC_INIT, "vce_ncnoc_init", 10,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_VCE_NCNOC_TARG, "vce_ncnoc_targ", 12,
+ JHB100_SYS0CLK_PLL1),
+ /* bmcperiph2 */
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_NCNOC_INIT, "bmcper2_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_NCNOC_TARG, "bmcper2_ncnoc_targ", 12,
+ JHB100_SYS0CLK_PLL1),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_CFG_400, "bmcper2_cfg_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_CFG_125, "bmcper2_cfg_125", 10,
+ JHB100_SYS0CLK_PLL1),
+ /* hostss1 */
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTSS1_NCNOC_DATA, "hostss1_ncnoc_data", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400, "hostss1_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0_GATE(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF,
+ "hostss1_phy_scan_400_icg_buf", CLK_IS_CRITICAL,
+ JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400),
+ /* npu */
+ JH71X0__DIV(JHB100_SYS0CLK_NPU_NCNOC_INIT, "npu_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* vout */
+ JH71X0__DIV(JHB100_SYS0CLK_VOUT_NCNOC_INIT, "vout_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_VOUT_AUX, "vout_aux", 150,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph3 */
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER3_NCNOC_INIT, "bmcper3_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusb */
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTUSB_NCNOC_INIT, "hostusb_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusbcmn */
+ JH71X0__DIV(JHB100_SYS0CLK_HOSTUSBCMN_CFG_480, "hostusbcmn_cfg_480", 5,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph1 */
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER1_NCNOC_INIT, "bmcper1_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER1_CFG_800, "bmcper1_cfg_800", 4,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph0 */
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER0_NCNOC_INIT, "bmcper0_ncnoc_init", 6,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER0_CFG_400, "bmcper0_cfg_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ JH71X0__DIV(JHB100_SYS0CLK_BMCPER0_CFG_800, "bmcper0_cfg_800", 8,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu0 */
+ JH71X0__DIV(JHB100_SYS0CLK_GPU0_NCNOC_INIT, "gpu0_ncnoc_init", 10,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu1 */
+ JH71X0__DIV(JHB100_SYS0CLK_GPU1_NCNOC_INIT, "gpu1_ncnoc_init", 10,
+ JHB100_SYS0CLK_PLL0),
+};
+
+static const struct jh71x0_crg_domain_info jhb100_sys0crg_info = {
+ .clk_data = jhb100_sys0crg_clk_data,
+ .num_clk = ARRAY_SIZE(jhb100_sys0crg_clk_data),
+ .ext_clk = jhb100_sys0_ext_clk,
+ .num_ext_clk = ARRAY_SIZE(jhb100_sys0_ext_clk),
+ .rst_name = "jhb100-r-sys0",
+ .power_domain = false,
+};
+
+static const struct of_device_id jhb100_sys0crg_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0crg",
+ .data = &jhb100_sys0crg_info,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys0crg_driver = {
+ .probe = jh71x0_crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-sys0",
+ .of_match_table = jhb100_sys0crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(jhb100_sys0crg_driver);
--
2.25.1
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