[RFC PATCH 0/2] drm: add a noncoherent mapping checking helper

[Icenowy Zheng]

This patchset tries to address the lack of uncached mapping support on
several SiFive-core-based SoCs, currently targeting JH7110 but EIC7700
would have the same problem (although it uses DC8000 display controller
instead of DC8200 and real display support is pending).

Because other users (either SoCs with Xuantie cores, which have
Xtheadmae extensions or non-RISC-V SoCs) of the driver have proper
writecombine support, a helper is added to check whether coherent
(cache-bypassing) mapping is available. This helper currently returns
true for all architectures except RISC-V, and checks whether
pgprot_writecombine() is a no-op on RISC-V.

The patch really enabling manual cache maintenance for the verisilicon
driver is picked from Dominique, and reworked to check both
dma-noncoherent property and the platform's mapping capaibility.

Tested on VisionFive 2 with the display enablement patchset at [1] (and
its dependency).

Also tested on Lichee Pi 4A (TH1520, which has Xtheadmae), operation is
not affected, map_noncoherent isn't set and Xorg says kernel dirty
updates aren't required.

[1] https://patch.msgid.link/20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com

Dominique Belhachemi (1):
  drm: verisilicon: support non-coherent DMA framebuffers

Icenowy Zheng (1):
  drm: add a helper function to check availbility of coherent mapping

 drivers/gpu/drm/verisilicon/vs_cursor_plane.c |  9 ++++++
 drivers/gpu/drm/verisilicon/vs_drm.c          | 32 ++++++++++++++++++-
 drivers/gpu/drm/verisilicon/vs_drm.h          |  7 ++++
 .../gpu/drm/verisilicon/vs_primary_plane.c    |  9 ++++++
 include/drm/drm_cache.h                       | 21 ++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)

-- 
2.55.0