[PATCH v5 0/6] clk/reset: anlogic: add support for DR1V90 SoC

[Brian Masney]

On Thu, 14 May 2026 17:27:16 +0800, Junhui Liu wrote:
> clk/reset: anlogic: add support for DR1V90 SoC
> 
> Add Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC, as
> well as corresponding dts bindings and dts integration.
> 
> The CRU driver framework is built around the clock controller as the
> primary device, with the reset controller implemented as an auxiliary
> device. The clock part refers to the vendor's code [1] to determine the
> structure of the clock tree.
> 
> [...]

Applied, thanks!

[1/6] clk: correct clk_div_mask() return value for width == 32
      commit: f036decc4434323b47b58ad9508fe27d8c9087c2
[2/6] dt-bindings: clock: add Anlogic DR1V90 CRU
      commit: 155d900e4c7d124dfc1fef598fecc6d17a1ea693
[3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC
      commit: c4e2f5e69ba4298c10ab5a64525379ca48ca921e
[4/6] reset: anlogic: add support for Anlogic DR1V90 resets
      commit: 9fd565971072d2d7158e15178f84b0273e294e70
[5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
      commit: 7849521aaac26b17820642010ab7f7a222ec73d1
[6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry
      commit: 5795c6059d10afbc0fbcfe3cd95676be69b30bcb

Best regards,
-- 
Brian Masney <bmasney at redhat.com>