[PATCH v7 0/5] iommu/riscv: Enable MSI remapping and IOMMU_DMA

[Andrew Jones]

This series adds MSI remapping for IMSIC so a device's MSI target gets
translated the same way its DMA does, allowing RISC-V to enable IOMMU_DMA
and paging domains by default.

The IMSIC MSI target address changes with interrupt affinity, so every
possible target must be mapped before an affinity change can select it
in atomic context. The IMSIC driver prepares an ordered list of targets
with iommu_dma_prepare_msi_list() when allocating an IRQ. DMA-IOMMU maps
the list into one contiguous IOVA range and caches the base in the domain.
The MSI descriptor carries the base IOVA and mapping granule, allowing
IMSIC to compose the target address without allocating memory or looking
up IOMMU state during affinity changes.

Ordered-list mappings have their own cache, separate from the existing
single-page MSI cache. IOVA allocation, mapping and rollback are shared
between the two paths.

VFIO and iommufd support from v6[1] is deferred. This series does not
enable VFIO_IOMMU_TYPE1 or introduce an IOMMU_RESV_SW_MSI reservation.
I'll look into Nicolin's MSI-window configuration patches[2] in a
follow-on series and see if I can avoid introducing IOMMU_RESV_SW_MSI
entirely. Without that reservation, the legacy Type1 backend cannot
provide the MSI mappings it needs, so I'll try to support existing Type1
userspace through iommufd's compatibility interface. That path will need
automatic MSI IOVA allocation, since existing Type1 userspace won't issue
Nicolin's new ioctls.

LLM-based coding assistants were used during development for code
exploration, patch review, test execution, and drafting and editing
commit messages and this cover letter. I reviewed and finalized all
resulting code and text. Per-patch Assisted-by tags are omitted in
light of ongoing discussions about simplifying coding-assistant
attribution.

Thanks,
drew

[1] https://lore.kernel.org/all/20260925151659.419512-1-andrew.jones@oss.qualcomm.com/
[2] https://lore.kernel.org/linux-iommu/cover.1760487869.git.nicolinc@nvidia.com/

v7:
- Rebased on linux-iommu/next at 20bfd2575765
- Added deferred-attach handling to the list API
- Simplified ordered-list mapping to a cached base IOVA per domain,
  separate from the existing per-page cache [Robin]
- Shared IOVA allocation, mapping and rollback between the list and
  single-page paths [Jason]
- Dropped the fixed MSI window in response to Jason's ABI concerns and
  deferred supporting VFIO Type1


Andrew Jones (4):
  iommu/dma: Prepare MSI physical address lists
  iommu/dma: Introduce iommu_dma_prepare_msi_list()
  irqchip/riscv-imsic: Add MSI address list
  irqchip/riscv-imsic: Support IOMMU MSI address lists

Tomasz Jeznach (1):
  iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V

 drivers/iommu/Kconfig                      |  2 +-
 drivers/iommu/dma-iommu.c                  | 77 ++++++++++++++++++++--
 drivers/iommu/dma-iommu.h                  | 10 +++
 drivers/iommu/iommu.c                      | 43 ++++++++++++
 drivers/irqchip/Kconfig                    |  1 +
 drivers/irqchip/irq-riscv-imsic-platform.c | 24 ++++++-
 drivers/irqchip/irq-riscv-imsic-state.c    | 32 +++++++++
 drivers/irqchip/irq-riscv-imsic-state.h    |  3 +
 include/linux/iommu.h                      |  9 +++
 9 files changed, 190 insertions(+), 11 deletions(-)

-- 
2.56.0