[PATCH] cache: sifive_ccache: Enable all ways when no LIM is reserved

[Pinkesh Vaghela]

Hi Conor,
 
On Wed, Oct 21, 2026 at 10:43 PM +0530, Conor Dooley wrote:
> On Wed, Oct 21, 2026 at 06:39:06PM +0530, Pinkesh Vaghela wrote:
> > The composable cache resets with only way 0 enabled, while the
> > remaining ways are available as Loosely Integrated Memory (LIM).
> > Systems that do not reserve LIM therefore use only one cache way
> > unless software increases WayEnable.
> 
> This is not true in the general case, firmware may intercede to set the ways as
> it pleases.
> 
> > When no memory-region property is present, DT describes no LIM
> > reservation for the cache controller. Validate the reported way count,
> > then enable all cache ways so Linux can use the full cache capacity.
> >
> > When memory-region is present, leave WayEnable unchanged because
> > enabled ways cannot be returned to LIM until reset. This may leave
> > more ways assigned to LIM than required, but avoids consuming reserved
> LIM.
> >
> > Apply this policy to all compatibles handled by the driver. Firmware
> > or
> 
> I know this is going to cause problems for all the microchip boards, which
> maybe should have reserved LIM but never did because the LIM was never
> put in the devicetree as memory in the first place.
> They also don't suffer from the problem you mention because firmware sets
> the ways up.
> 
> > DT configurations that require LIM must provide memory-region;
> > otherwise, Linux will convert all disabled ways to cache.
> 
> I don't like this behavioural change, it's never been mandatory to have a
> reserved memory region for the LIM. I'm only in favour of doing this on
> devices where we know it is actually required to be done. The eic7700 I
> assume is one such device.
> 
> Cheers,
> Conor.

Thanks for pointing this out.
 
I agree that firmware may have already configured the cache/LIM
partition, so applying this behavior generally could overwrite that
configuration.
 
EIC7700 firmware does not enable the additional cache ways, leaving
only way 0 enabled when no LIM is reserved.
 
I will restrict the change to EIC7700 using a device-specific quirk
while retaining the memory-region check. Would this approach be
acceptable?
 
Regards,
Pinkesh

> 
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela at einfochips.com>
> > ---
> >  drivers/cache/sifive_ccache.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/drivers/cache/sifive_ccache.c
> > b/drivers/cache/sifive_ccache.c index 2acb8bdf06d5..17b6ba8ab984
> > 100644
> > --- a/drivers/cache/sifive_ccache.c
> > +++ b/drivers/cache/sifive_ccache.c
> > @@ -117,6 +117,22 @@ static void ccache_config_read(void)
> >  	pr_info("Index of the largest way enabled: %u\n", cfg);  }
> >
> > +static int ccache_enable_all_ways(void) {
> > +	u32 config, ways;
> > +
> > +	config = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> > +	ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, config);
> > +	if (!ways) {
> > +		pr_err("Invalid cache configuration: zero ways\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	writel(ways - 1, ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > +
> > +	return 0;
> > +}
> > +
> >  static const struct of_device_id sifive_ccache_ids[] = {
> >  	{ .compatible = "eswin,eic7700-l3-cache",
> >  	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) }, @@ -319,6
> +335,12
> > @@ static int __init sifive_ccache_init(void)
> >  		goto err_unmap;
> >  	}
> >
> > +	if (!of_property_present(np, "memory-region")) {
> > +		rc = ccache_enable_all_ways();
> > +		if (rc)
> > +			goto err_unmap;
> > +	}
> > +
> >  #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
> >  	if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
> >  		riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
> > --
> > 2.34.1
> >