[PATCH v6 10/16] irqchip/riscv-imsic: Add MSI address list

[Thomas Gleixner]

On Fri, Sep 25 2026 at 17:16, Andrew Jones wrote:
> Upcoming RISC-V IOMMU interrupt remapping needs to map every possible
> host IMSIC target into one contiguous MSI IOVA range. MSI message
> composition then uses the target CPU's position within that range.
>
> Build an IMSIC physical address array indexed by logical CPU.
> Require every possible CPU to have an initialized IMSIC page before
> publishing the array. This preserves physical address zero as a valid
> target and guarantees the array has num_possible_cpus() entries.
>
> The array size and each target's index can therefore be derived
> directly, without storing duplicate count or per-CPU index metadata.
>
> Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> Tested-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>

Acked-by: Thomas Gleixner <tglx at kernel.org>