[PATCH v6 09/16] iommu/riscv: Reserve an MSI IOVA window for iommufd

[Jason Gunthorpe]

> iommufd requires an IOMMU_RESV_SW_MSI region to allocate stable IOVAs
> for MSI targets. Advertise such a region when the device uses an IMSIC
> MSI hierarchy so interrupt remapping can map IMSIC pages instead of
> falling back to physical addresses.

This commit message is close to useless. Please describe how this
range is actually used, including how the guest would interact with
it.

> Reserve one page per possible CPU, sufficient for each supervisor IMSIC
> page. Use a 16 MiB base instead of the 128 MiB convention used by ARM
> SMMU. kvmtool places its guest IMSIC at 128 MiB, so with IRQ bypass the
> domain-wide guest MSI address match can also capture host-delivered
> MSI writes to the SW MSI window and misdeliver them to the guest.
> 
> 16 MiB falls in a hole in the current kvmtool and QEMU virt memory maps,
> away from their guest IMSIC windows and RAM. Keep the window below
> 4 GiB so devices with 32-bit MSI address registers can use it.

And this is a good reason you should not follow ARM down this mad
road. Nicolin had some patches to allow userspace to select the SW_MSI
range instead of using a kernel hard coded value, which becomes a
sneaky ABI. It would be much better if riscv starts off on the right
foot instead of continuing this mistake.

-- 
Jason