[PATCH v5 7/7] riscv: dts: eswin: add watchdog support

Pinkesh Vaghela pinkesh.vaghela at einfochips.com
Thu Oct 15 05:54:54 PDT 2026


From: Pritesh Patel <pritesh.patel at einfochips.com>

EIC7700 have four DesignWare watchdog controllers that are
integrated to SoC.

The controllers use only SoC-internal register, interrupt, clock and
reset resources and have no board-level dependencies, so describe them
as available in the SoC DTSI.

Each watchdog counter is driven by its corresponding LSP APB clock.
The NOC_WDREF clock belongs to the separate NoC watchdog and is not
used by these controller instances.

Signed-off-by: Pritesh Patel <pritesh.patel at einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela at einfochips.com>
---
 arch/riscv/boot/dts/eswin/eic7700.dtsi | 36 ++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c0aa91b357ff..ec58a3aaf582 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -265,6 +265,42 @@ syscon: syscon at 50440000 {
 			};
 		};
 
+		wdt0: watchdog at 50800000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50800000 0x0 0x4000>;
+			interrupts = <87>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT0>;
+		};
+
+		wdt1: watchdog at 50804000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50804000 0x0 0x4000>;
+			interrupts = <88>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT1>;
+		};
+
+		wdt2: watchdog at 50808000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50808000 0x0 0x4000>;
+			interrupts = <89>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT2>;
+		};
+
+		wdt3: watchdog at 5080c000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x5080c000 0x0 0x4000>;
+			interrupts = <90>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT3>;
+		};
+
 		uart0: serial at 50900000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x50900000 0x0 0x10000>;
-- 
2.34.1




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