[PATCH v7 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask

[Drew Fustini]

On Tue, Oct 13, 2026 at 02:29:41PM -0700, Reinette Chatre wrote:
> Hi Tony,
> 
> On 10/13/26 1:47 PM, Luck, Tony wrote:
[..]
> > Don't bother with a control_mode to switch between legacy and native.
> > Just auto-select the "L2A" control on asymmetric systems.
> > 
> > But since this thread started from a RISC-V thread, it would be good to
> > hear what is needed for RISC-V.
> ack.

For RISC-V CBQRI, the number of capacity blocks (NCBLKS) is a field of
each controller's cc_capabilities register, so two controllers at one
cache level can report different values. This series will leave a level
unexposed if NCBLKS differs. The per-domain max would allow such
controllers to be fully represented in resctrl.

The hardware I am working with (Ascalon shared cache) has only a single
NCBLKS value, and I am not aware of any RISC-V hardware with different
NCBLKS at the same cache level. Therefore, I don't think it is an
immediate concern, but the spec does make it possible for asymmetric
systems to emerge in the future. It would probably be reasonable to
require native controls to be used for such systems.

Thanks,
Drew