[External] Re: [PATCH v4 0/5] Add workarounds for Picoheart erratas

[yunhui cui]

Hi Yicong,

On Mon, Oct 12, 2026 at 2:42 PM Yicong Yang <yang.yicong at picoheart.com> wrote:
>
> a gentle ping for this patchset...
>
> thanks.

  Thanks for the series. Two issues found in v4:

  1. The CBO erratum uses MMU-only uaccess helpers, so the NOMMU build
     currently fails. Could ERRATA_PICOHEART_CBO_CLEAN depend on MMU?
     Using unsigned long for addr would also avoid the RV32 warning.

  2. SR_MXR remains enabled across get_user(), whose might_fault() may
     schedule. Would it be safer to prepare for the fault first, then use
     __get_user() with MXR enabled and restore the original MXR state?

  Thanks,
  Yunhui

>
> On 9/15/26 4:33 PM, Yicong Yang wrote:
> > This series add basic errata framework for Picoheart SoCs for handling
> > upcoming Picoheart erratas. And add workarounds for the first two
> > erratas on our hardware. Also do some fixups and refactor in support
> > of the erratas.
> >
> > Change since v3:
> > - workaround CASQ by patching the system_support_cmpxhg128()
> > Link: https://lore.kernel.org/linux-riscv/20260907072149.72031-1-yang.yicong@picoheart.com/
> >
> > Change since v2:
> > - rebase on 7.3-rc2
> > - merge the MXR fix and get_insn extraction into one patch
> > Link: https://lore.kernel.org/linux-riscv/20260728094627.94975-1-yang.yicong@picoheart.com/
> >
> > Change since v1:
> > - factor out a common get_insn for reading userspace instructions
> > - fix the issue from reading instructions of a exec-only mapping
> > - cleanups and code style refinements per comments
> > Link: https://lore.kernel.org/linux-riscv/20260715084724.26578-1-yang.yicong@picoheart.com/
> >
> > Yicong Yang (5):
> >   riscv: Make get_insn public for instruction fault handling
> >   riscv: insn: Support decoding of CBO instructions
> >   riscv: errata: Add init framework for picoheart errata
> >   riscv: errata: picoheart: Add workaround for cbo.clean errata
> >   riscv: errata: picoheart: Add workaround for AMOCASQ errata
> >
> >  arch/riscv/Kconfig.errata                    |  34 +++
> >  arch/riscv/errata/Makefile                   |   1 +
> >  arch/riscv/errata/picoheart/Makefile         |   5 +
> >  arch/riscv/errata/picoheart/errata.c         | 242 +++++++++++++++++++
> >  arch/riscv/include/asm/alternative.h         |   3 +
> >  arch/riscv/include/asm/cmpxchg.h             |  21 +-
> >  arch/riscv/include/asm/csr.h                 |   1 +
> >  arch/riscv/include/asm/errata_list.h         |  25 +-
> >  arch/riscv/include/asm/errata_list_vendors.h |   5 +
> >  arch/riscv/include/asm/insn.h                |  63 ++++-
> >  arch/riscv/include/asm/processor.h           |   2 +-
> >  arch/riscv/include/asm/vendorid_list.h       |   1 +
> >  arch/riscv/kernel/alternative.c              |   5 +
> >  arch/riscv/kernel/asm-offsets.c              |   6 +-
> >  arch/riscv/kernel/cpufeature.c               |   3 +
> >  arch/riscv/kernel/entry.S                    |  14 +-
> >  arch/riscv/kernel/traps.c                    |   4 +
> >  arch/riscv/kernel/traps_misaligned.c         |  52 ----
> >  arch/riscv/kernel/vector.c                   |   6 +-
> >  19 files changed, 423 insertions(+), 70 deletions(-)
> >  create mode 100644 arch/riscv/errata/picoheart/Makefile
> >  create mode 100644 arch/riscv/errata/picoheart/errata.c