[PATCH] riscv: signal: protect regs->status RMW from concurrent preemption

[Zhang, Guobin]

On 2026-09-25, Aurelien Jarno wrote:
> As you also mention that you reproduced the issue on the Spacemit K1
> hardware, can you please tell me if the bug appeared with similar
> symptoms?

In my case, the issue manifested as a SIGILL coredump. The signal
information was:

    si_signo = 4 (SIGILL)
    si_code  = 1 (ILL_ILLOPC)

So the observed symptom was SIGILL/ILL_ILLOPC on SpacemiT K1.

Thanks,
Guobin