[PATCH v6 0/8] riscv: optimize mode switch latency for Vector

[Paul Walmsley]

On Tue, 6 Oct 2026, patchwork-bot+linux-riscv at kernel.org wrote:

> Hello:
> 
> This series was applied to riscv/linux.git (for-next)
> by Paul Walmsley <pjw at kernel.org>:
> 

[ ... ]

> Here is the summary with links:
>   - [v6,1/8] riscv: do not read csr in vector context switch
>     https://git.kernel.org/riscv/c/5fd018c630e2
>   - [v6,2/8] riscv: vector: refactor context switch for kernel-mode vector
>     https://git.kernel.org/riscv/c/4740b934ebe7
>   - [v6,3/8] selftest: riscv: test vectorized user copy
>     https://git.kernel.org/riscv/c/52318cf0fa6e
>   - [v6,4/8] riscv: vector: refactor vector context operations
>     https://git.kernel.org/riscv/c/1a5c75ee3d09
>   - [v6,5/8] riscv: clarify vector state semantics on syscall and context switch
>     https://git.kernel.org/riscv/c/cc12e55016ba
>   - [v6,6/8] riscv: vector: adjust ptrace and signal behavior for INITIAL state
>     https://git.kernel.org/riscv/c/0d4b43a7734d
>   - [v6,7/8] selftests: riscv: Extend vector tests for sigreturn and ptrace
>     https://git.kernel.org/riscv/c/6740ec489dd7
>   - [v6,8/8] riscv: vector: optimize vstate operations
>     (no matching commit)

Just to clarify, I only applied the first three patches, for the reason
mentioned earlier.


- Paul