[PATCH] riscv: align pcie bus assign logic with ARM64

[Paul Walmsley]

Hi,

Thanks for updating the patch.  A few comments:

On Tue, 29 Sep 2026, sun.wenhan at zte.com.cn wrote:

> RISC-V currently relies on the asm-generic default of
> pcibios_assign_all_busses() returning 1, so the kernel always
> re-assigns all PCI bus numbers and ignores the bus numbers already
> set up by the firmware. This has two downsides.
> 
> As UEFI 2.8 has brought mature firmware support to RISC-V servers,
> the OS can trust and inherit the PCI bus enumeration done by the
> BIOS, skipping a redundant re-enumeration at boot and improving the
> boot time.
> 
> The unconditional re-assignment also causes bus numbering conflicts
> during PCI rescan. When a root port that is not the last one in the
> hierarchy is removed and the bus is rescanned, the kernel fails
> with:
> 
>     pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under
>     [bus 00-ff] (conflicts with (null) [bus 02])
> 
> Define pcibios_assign_all_busses() the same way as ARM64, so that
> RISC-V also preserves the bus numbers assigned by the firmware by
> default instead of always re-assigning them. This keeps RISC-V
> consistent with the other major architectures.
> 
> Signed-off-by: sun wenhan <sun.wenhan at zte.com.cn>

- Please start your subject line with "[PATCH v2]" etc. when sending 
  updated versions of patches.  Please see
  https://www.kernel.org/doc/html/latest/process/submitting-patches.html#subject-line

- Some tools break when the name in your E-mail is an E-mail address.  I 
  fixed this up to match the same in your Signed-off-by:, but please fix 
  this for future patches.

Queued for v7.4, thanks.


- Paul