[PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC
Mina Hui-Min Chou
minachou at andestech.com
Thu Nov 12 23:11:27 PST 2026
Rename all L2-related identifiers to LLC to accurately reflect the
cache's role as the system's last-level cache.
This is a mechanical rename with no functional change:
- macros: ANDES_L2C_* -> ANDES_LLC_*
- struct: l2c_base -> llc_base
- function: andes_*_l2_*() -> andes_*_llc_*()
- comments: L2 cache -> LLC
Signed-off-by: Mina Hui-Min Chou <minachou at andestech.com>
---
drivers/cache/ax45mp_cache.c | 80 ++++++++++++++++++------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 4f9b8a9ad969..0ee8218d5a82 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -13,36 +13,36 @@
#include <asm/dma-noncoherent.h>
-/* L2 cache registers */
-#define ANDES_L2C_REG_CTL_OFFSET 0x8
+/* LLC registers */
+#define ANDES_LLC_REG_CTL_OFFSET 0x8
-#define ANDES_L2C_REG_C0_CMD_OFFSET 0x40
-#define ANDES_L2C_REG_C0_ACC_OFFSET 0x48
-#define ANDES_L2C_REG_STATUS_OFFSET 0x80
+#define ANDES_LLC_REG_C0_CMD_OFFSET 0x40
+#define ANDES_LLC_REG_C0_ACC_OFFSET 0x48
+#define ANDES_LLC_REG_STATUS_OFFSET 0x80
/* D-cache operation */
#define ANDES_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */
#define ANDES_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
-/* L2 CCTL status */
-#define ANDES_CCTL_L2_STATUS_IDLE 0
+/* LLC CCTL status */
+#define ANDES_CCTL_LLC_STATUS_IDLE 0
-/* L2 CCTL status cores mask */
-#define ANDES_CCTL_L2_STATUS_C0_MASK 0xf
+/* LLC CCTL status cores mask */
+#define ANDES_CCTL_LLC_STATUS_C0_MASK 0xf
-/* L2 cache operation */
-#define ANDES_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */
-#define ANDES_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
+/* LLC operation */
+#define ANDES_CCTL_LLC_PA_INVAL 0x8 /* Invalidate an LLC entry */
+#define ANDES_CCTL_LLC_PA_WB 0x9 /* Write-back an LLC entry */
-#define ANDES_L2C_REG_PER_CORE_OFFSET 0x10
-#define ANDES_CCTL_L2_STATUS_PER_CORE_OFFSET 4
+#define ANDES_LLC_REG_PER_CORE_OFFSET 0x10
+#define ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET 4
-#define ANDES_L2C_REG_CN_CMD_OFFSET(n) \
- (ANDES_L2C_REG_C0_CMD_OFFSET + ((n) * ANDES_L2C_REG_PER_CORE_OFFSET))
-#define ANDES_L2C_REG_CN_ACC_OFFSET(n) \
- (ANDES_L2C_REG_C0_ACC_OFFSET + ((n) * ANDES_L2C_REG_PER_CORE_OFFSET))
-#define ANDES_CCTL_L2_STATUS_CN_MASK(n) \
- (ANDES_CCTL_L2_STATUS_C0_MASK << ((n) * ANDES_CCTL_L2_STATUS_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CN_CMD_OFFSET(n) \
+ (ANDES_LLC_REG_C0_CMD_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CN_ACC_OFFSET(n) \
+ (ANDES_LLC_REG_C0_ACC_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
+#define ANDES_CCTL_LLC_STATUS_CN_MASK(n) \
+ (ANDES_CCTL_LLC_STATUS_C0_MASK << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
#define ANDES_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b
#define ANDES_CCTL_REG_UCCTLCOMMAND_NUM 0x80c
@@ -50,23 +50,23 @@
#define ANDES_CACHE_LINE_SIZE 64
struct andes_priv {
- void __iomem *l2c_base;
+ void __iomem *llc_base;
u32 andes_cache_line_size;
};
static struct andes_priv andes_priv;
-/* L2 Cache operations */
-static inline uint32_t andes_cpu_l2c_get_cctl_status(void)
+/* LLC operations */
+static inline uint32_t andes_cpu_llc_get_cctl_status(void)
{
- return readl(andes_priv.l2c_base + ANDES_L2C_REG_STATUS_OFFSET);
+ return readl(andes_priv.llc_base + ANDES_LLC_REG_STATUS_OFFSET);
}
static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
- unsigned int l1_op, unsigned int l2_op)
+ unsigned int l1_op, unsigned int llc_op)
{
unsigned long line_size = andes_priv.andes_cache_line_size;
- void __iomem *base = andes_priv.l2c_base;
+ void __iomem *base = andes_priv.llc_base;
int mhartid = smp_processor_id();
unsigned long pa;
@@ -75,29 +75,29 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
csr_write(ANDES_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
pa = virt_to_phys((void *)start);
- writel(pa, base + ANDES_L2C_REG_CN_ACC_OFFSET(mhartid));
- writel(l2_op, base + ANDES_L2C_REG_CN_CMD_OFFSET(mhartid));
- while ((andes_cpu_l2c_get_cctl_status() &
- ANDES_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
- ANDES_CCTL_L2_STATUS_IDLE)
+ writel(pa, base + ANDES_LLC_REG_CN_ACC_OFFSET(mhartid));
+ writel(llc_op, base + ANDES_LLC_REG_CN_CMD_OFFSET(mhartid));
+ while ((andes_cpu_llc_get_cctl_status() &
+ ANDES_CCTL_LLC_STATUS_CN_MASK(mhartid)) !=
+ ANDES_CCTL_LLC_STATUS_IDLE)
;
start += line_size;
}
}
-/* Write-back L1 and L2 cache entry */
+/* Write-back L1 and LLC entry */
static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
{
andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_WB,
- ANDES_CCTL_L2_PA_WB);
+ ANDES_CCTL_LLC_PA_WB);
}
-/* Invalidate the L1 and L2 cache entry */
+/* Invalidate the L1 and LLC entry */
static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
{
andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_INVAL,
- ANDES_CCTL_L2_PA_INVAL);
+ ANDES_CCTL_LLC_PA_INVAL);
}
static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
@@ -146,7 +146,7 @@ static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
andes_dma_cache_inv(paddr, size);
}
-static int andes_get_l2_line_size(struct device_node *np)
+static int andes_get_llc_line_size(struct device_node *np)
{
int ret;
@@ -200,13 +200,13 @@ static int __init andes_cache_init(void)
if (!riscv_cbom_block_size)
return 0;
- andes_priv.l2c_base = ioremap(res.start, resource_size(&res));
- if (!andes_priv.l2c_base)
+ andes_priv.llc_base = ioremap(res.start, resource_size(&res));
+ if (!andes_priv.llc_base)
return -ENOMEM;
- ret = andes_get_l2_line_size(np);
+ ret = andes_get_llc_line_size(np);
if (ret) {
- iounmap(andes_priv.l2c_base);
+ iounmap(andes_priv.llc_base);
return ret;
}
--
2.34.1
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