[PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support

[Mina Hui-Min Chou]

The last level cache controller of Andes cores is not specific to
AX45MP. Other Andes cores, such as the A27L2, use the same controller
with the same register interface, but the binding only accepts
andestech,ax45mp-cache. Add andestech,llcache for them, and describe
the binding as an Andes last level cache rather than an AX45MP L2
cache.

The cache-level, cache-sets and cache-size constraints describe the
AX45MP L2 cache, so apply them to andestech,ax45mp-cache only. The LLC
of other Andes cores can be level 3 and have other geometries, so
allow cache-level 3 and require cache-sets only for AX45MP. Match
renesas,r9a07g043f-ax45mp-cache explicitly instead of through the else
branch, which would otherwise also apply to andestech,llcache.

Also add an example for andestech,llcache, and add myself as a
maintainer of the binding.

Signed-off-by: Mina Hui-Min Chou <minachou at andestech.com>
---
 .../cache/andestech,ax45mp-cache.yaml         | 71 ++++++++++++++-----
 1 file changed, 54 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index b135ffa4ab6b..da9688cc95f7 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -5,14 +5,15 @@
 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Andestech AX45MP L2 Cache Controller
+title: Andestech Last Level Cache Controller
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
+  - Mina Hui-Min Chou <minachou at andestech.com>
 
 description:
-  A level-2 cache (L2C) is used to improve the system performance by providing
-  a large amount of cache line entries and reasonable access delays. The L2C
+  A last level cache (LLC) is used to improve the system performance by providing
+  a large amount of cache line entries and reasonable access delays. The LLC
   is shared between cores, and a non-inclusive non-exclusive policy is used.
 
 select:
@@ -21,18 +22,23 @@ select:
       contains:
         enum:
           - andestech,ax45mp-cache
+          - andestech,llcache
 
   required:
     - compatible
 
 properties:
   compatible:
-    items:
-      - enum:
-          - andestech,qilai-ax45mp-cache
-          - renesas,r9a07g043f-ax45mp-cache
-      - const: andestech,ax45mp-cache
-      - const: cache
+    oneOf:
+      - items:
+          - enum:
+              - andestech,qilai-ax45mp-cache
+              - renesas,r9a07g043f-ax45mp-cache
+          - const: andestech,ax45mp-cache
+          - const: cache
+      - items:
+          - const: andestech,llcache
+          - const: cache
 
   reg:
     maxItems: 1
@@ -44,13 +50,11 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
-  cache-sets:
-    enum: [1024, 2048]
+  cache-sets: true
 
-  cache-size:
-    enum: [131072, 262144, 524288, 1048576, 2097152]
+  cache-size: true
 
   cache-unified: true
 
@@ -64,7 +68,6 @@ required:
   - interrupts
   - cache-line-size
   - cache-level
-  - cache-sets
   - cache-size
   - cache-unified
 
@@ -73,15 +76,36 @@ allOf:
       properties:
         compatible:
           contains:
-            const: andestech,qilai-ax45mp-cache
+            const: andestech,ax45mp-cache
+    then:
+      properties:
+        cache-level:
+          const: 2
+        cache-sets:
+          enum: [1024, 2048]
+        cache-size:
+          enum: [131072, 262144, 524288, 1048576, 2097152]
+      required:
+        - cache-sets
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: andestech,qilai-ax45mp-cache
     then:
       properties:
         cache-sets:
           const: 2048
         cache-size:
           const: 2097152
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043f-ax45mp-cache
+    then:
       properties:
         cache-sets:
           const: 1024
@@ -101,3 +125,16 @@ examples:
         cache-size = <262144>;
         cache-unified;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    cache-controller at e0500000 {
+        compatible = "andestech,llcache", "cache";
+        reg = <0xe0500000 0x10000>;
+        interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+        cache-line-size = <64>;
+        cache-level = <2>;
+        cache-size = <262144>;
+        cache-unified;
+    };
-- 
2.34.1