[PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers

[Mina Hui-Min Chou]

The LLC has a separate set of CCTL registers for each core, selected by
the hart ID of the core. The driver selects the set with
smp_processor_id(), which returns the logical CPU number, not the hart
ID.

The two numbers differ when some harts are not used by Linux, or when
Linux boots on a hart other than 0, as the boot hart is always CPU 0.
A CPU then issues its LLC operations through the registers of another
hart, which may be in use by that hart at the same time.

RZ/Five has a single core with hart ID 0, so the two numbers always
match there and the problem never showed up.

Convert the logical CPU number to the hart ID with
cpuid_to_hartid_map().

Signed-off-by: Mina Hui-Min Chou <minachou at andestech.com>
---
 drivers/cache/andes_llcache.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 80c55616ab10..9f8fa8964302 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -65,7 +65,7 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 {
 	unsigned long line_size = andes_priv.andes_cache_line_size;
 	void __iomem *base = andes_priv.llc_base;
-	int mhartid = smp_processor_id();
+	unsigned long hartid = cpuid_to_hartid_map(smp_processor_id());
 	phys_addr_t pa;
 
 	while (end > start) {
@@ -74,10 +74,10 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 
 		pa = virt_to_phys((void *)start);
 		/* The access line register is 64 bits; written lo-hi on RV32 */
-		writeq(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
-		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
+		writeq(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(hartid));
+		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(hartid));
 		while ((andes_cpu_llc_get_cctl_status() &
-			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
+			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(hartid)) !=
 			ANDES_LLC_CCTL_STATUS_IDLE)
 			;
 
-- 
2.34.1